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<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89549338/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89549338/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">JEDEC </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls1 ws0">STANDARD </div><div class="t m0 x1 h2 y3 ff1 fs0 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h2 y4 ff1 fs0 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h3 y5 ff1 fs1 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h4 y6 ff1 fs2 fc0 sc0 ls3 ws1">DDR4 SDRAM </div><div class="t m0 x1 h4 y7 ff1 fs2 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h4 y8 ff1 fs2 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h4 y9 ff1 fs2 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h4 ya ff1 fs2 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h3 yb ff1 fs1 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h4 yc ff1 fs2 fc0 sc0 ls4 ws0">JESD79-4B<span class="ff2 ls2"> </span></div><div class="t m0 x1 h5 yd ff2 fs3 fc0 sc0 ls5 ws2">(Revision of JESD79-4A, November 2013) </div><div class="t m0 x1 h5 ye ff2 fs3 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h5 yf ff2 fs3 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h5 y10 ff2 fs3 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h5 y11 ff2 fs3 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h5 y12 ff2 fs3 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h5 y13 ff2 fs3 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h6 y14 ff1 fs4 fc0 sc0 ls6 ws3">JUNE 2017 </div><div class="t m0 x1 h7 y15 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h7 y16 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h8 y17 ff2 fs5 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1 h9 y18 ff1 fs5 fc0 sc0 ls7 ws4">JEDEC SOLID STATE TECHNOLOGY ASSOCIATION </div><div class="t m0 x1 ha y19 ff1 fs6 fc0 sc0 ls2 ws0"> </div><div class="t m0 x2 h7 y1a ff2 fs4 fc0 sc0 ls8 ws0"> <span class="_ _0"></span> </div><div class="t m0 x3 hb y1b ff3 fs7 fc1 sc0 ls2 ws0"><span class="fc2 sc0">Downloaded by ?? ? (zhenlong.yan@keysight.com) on Jul 29, 2019, 7:34 pm PDT</span></div><div class="t m1 x4 hc y1c ff3 fs8 fc1 sc0 ls2 ws0"><span class="fc2 sc0">keysight</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89549338/bg2.jpg"><div class="t m0 x5 h7 y1d ff2 fs4 fc0 sc0 ls9 ws0">NOTICE </div><div class="t m0 x6 h7 y1e ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x7 h7 y1f ff2 fs4 fc0 sc0 lsa ws5">JEDEC standards and publications contain material that has been prepared, reviewed, and </div><div class="t m0 x8 h7 y20 ff2 fs4 fc0 sc0 ls3 ws1">approved through the JEDEC Board of Directors le<span class="lsb ws6">vel and subsequently reviewed and approved </span></div><div class="t m0 x9 h7 y21 ff2 fs4 fc0 sc0 ls3 ws1">by the JEDEC legal counsel. </div><div class="t m0 x6 h7 y22 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 xa h7 y23 ff2 fs4 fc0 sc0 lsc ws7">JEDEC standards and publications are designed to serve the public interest through eliminating </div><div class="t m0 xb h7 y24 ff2 fs4 fc0 sc0 lsc ws7">misunderstandings between manufacturers and purchasers, facilitating interchangeability and </div><div class="t m0 xa h7 y25 ff2 fs4 fc0 sc0 lsa ws5">improvement of products, and assisting the purch<span class="lsc ws7">aser in selecting and obtaining with m<span class="_ _1"></span>inimum </span></div><div class="t m0 xc h7 y26 ff2 fs4 fc0 sc0 lsa ws5">delay the proper product for use by those other than JEDEC members, whether the standard is to </div><div class="t m0 xd h7 y27 ff2 fs4 fc0 sc0 lsd ws8">be used either domestically or internationally. </div><div class="t m0 x6 h7 y28 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 xe h7 y29 ff2 fs4 fc0 sc0 lsb ws6">JEDEC standards and publications are adopted wit<span class="lsc ws7">hout regard to whether or not their adoption </span></div><div class="t m0 xf h7 y2a ff2 fs4 fc0 sc0 lsd ws8">may involve patents or articles, materials, or <span class="lse ws9">processes. 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Within the JEDEC organization there <span class="lsf wsa">are procedures whereby a JEDEC standard or </span></div><div class="t m0 x13 h7 y31 ff2 fs4 fc0 sc0 lsc ws7">publication may be further processed and ultim<span class="_ _1"></span>ately become an ANSI standard. </div><div class="t m0 x6 h7 y32 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x14 h7 y33 ff2 fs4 fc0 sc0 lsc ws7">No claims to be in conformance with this standard m<span class="_ _1"></span>ay be made unless all requirements stated in </div><div class="t m0 x15 h7 y34 ff2 fs4 fc0 sc0 lsd ws8">the standard are met. </div><div class="t m0 x6 h7 y35 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x16 h7 y36 ff2 fs4 fc0 sc0 lsa ws5">Inquiries, comments, and suggestions relative to the content of this JEDEC standard or </div><div class="t m0 x14 h7 y37 ff2 fs4 fc0 sc0 lsa ws5">publication should be addressed to JEDEC at the address below, or refer to <span class="fc3 ls10 ws0">www.jedec.org</span> under </div><div class="t m0 x17 h7 y38 ff2 fs4 fc0 sc0 lsc ws7">Standards and Documents for alternative contact information. </div><div class="t m0 x6 h7 y39 ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x18 h7 y3a ff2 fs4 fc0 sc0 ls3 ws1">Published by </div><div class="t m0 x19 h7 y3b ff2 fs4 fc0 sc0 ls3 ws1">©JEDEC Solid State Technology Association 2017 </div><div class="t m0 x1a h7 y3c ff2 fs4 fc0 sc0 lsf wsa">3103 North 10th Street </div><div class="t m0 x1b h7 y3d ff2 fs4 fc0 sc0 lse ws9">Suite 240 South </div><div class="t m0 x1c h7 y3e ff2 fs4 fc0 sc0 ls10 wsb">Arlington, VA 22201-2107 </div><div class="t m0 x6 h7 y3f ff2 fs4 fc0 sc0 ls2 ws0"> </div><div class="t m0 x1d h7 y40 ff2 fs4 fc0 sc0 ls3 ws1">This document may be downloaded free of charge; however JEDEC retains the </div><div class="t m0 x1e h7 y41 ff2 fs4 fc0 sc0 lsc ws7">copyright on this material. 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(zhenlong.yan@keysight.com) on Jul 29, 2019, 7:34 pm PDT</span></div><div class="t m1 x4 hc y1c ff3 fs8 fc1 sc0 ls2 ws0"><span class="fc2 sc0">keysight</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89549338/bg4.jpg"><div class="t m0 x3 hb y1b ff3 fs7 fc1 sc0 ls2 ws0"><span class="fc2 sc0">Downloaded by ?? ? (zhenlong.yan@keysight.com) on Jul 29, 2019, 7:34 pm PDT</span></div><div class="t m1 x4 hc y1c ff3 fs8 fc1 sc0 ls2 ws0"><span class="fc2 sc0">keysight</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89549338/bg5.jpg"><div class="t m0 x2b he y4c ff4 fs9 fc0 sc0 ls19 ws0">JEDEC Standard No. 79-4B</div><div class="t m0 x2c hf y4d ff4 fsa fc0 sc0 ls1a ws0">-i-</div><div class="t m0 x2d h10 y4e ff5 fsb fc0 sc0 ls1b ws0">1<span class="_ _2"> </span>Scope<span class="_ _3"> </span>..........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="ls1c">..........<span class="_ _1"></span>................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.......<span class="_ _4"></span>1</span></div><div class="t m0 x2d h10 y4f ff5 fsb fc0 sc0 ls1d ws0">2<span class="_ _2"> </span>DDR4 SDRAM Package Pinout and <span class="ls1e">Addressing <span class="_ _3"> </span>.....<span class="ls1f">................<span class="ls1c">.<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _1"></span>.............<span class="_ _4"></span>2</span></span></span></div><div class="t m0 x2d h11 y50 ff4 fsb fc0 sc0 ls20 ws0">2.1 <span class="_ _5"> </span>DDR4 SDRAM Row for X4, X8 <span class="ls21">and X16<span class="_ _6"></span>........<span class="ls1f">........<span class="ls22">.........<span class="ls1c">...<span class="_ _1"></span>..............</span></span></span></span></div><div class="t m0 x2e h11 y51 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="_ _4"></span>2</div><div class="t m0 x2d h11 y52 ff4 fsb fc0 sc0 ls6 ws0">2.2 <span class="_ _5"> </span>DDR4 SDRAM Ball Pitch<span class="_ _3"> </span>....<span class="lse">......................<span class="ls1f">............<span class="ls1c">........<span class="_ _1"></span>..............<span class="_ _1"></span>...</span></span></span></div><div class="t m0 x2f h11 y53 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..........<span class="_ _1"></span>............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="_ _4"></span>2</div><div class="t m0 x2d h11 y54 ff4 fsb fc0 sc0 ls23 ws0">2.3 <span class="_ _5"> </span>DDR4 SDRAM Columns for X4,X<span class="ls24">8 and X16<span class="_ _4"></span>......<span class="ls1f">........<span class="ls22">.........<span class="ls1c">..............<span class="_ _1"></span>.....</span></span></span></span></div><div class="t m0 x30 h11 y55 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>.........<span class="_ _1"></span>..............<span class="_ _1"></span>.......<span class="_ _4"></span>2</div><div class="t m0 x2d h11 y56 ff4 fsb fc0 sc0 ls20 ws0">2.4 <span class="_ _5"> </span>DDR4 SDRAM X4/8 Ballout usi<span class="ls24">ng MO-20<span class="_ _4"></span>7<span class="_ _3"> </span>.......<span class="ls1f">................<span class="ls1c">...<span class="_ _1"></span>............</span></span></span></div><div class="t m0 x2e h11 y57 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _1"></span>..............<span class="_ _1"></span>..........<span class="_ _4"></span> 2</div><div class="t m0 x2d h11 y58 ff4 fsb fc0 sc0 ls20 ws0">2.5 <span class="_ _5"> </span>DDR4 SDRAM X16 Ballout usi<span class="ls25">ng MO-207<span class="_ _7"> </span>........<span class="ls1f">................<span class="ls1c">...<span class="_ _1"></span>............</span></span></span></div><div class="t m0 x2e h11 y59 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="_ _4"></span>3</div><div class="t m0 x2d h11 y5a ff4 fsb fc0 sc0 ls20 ws0">2.6 <span class="_ _5"> </span>DDR4 SDRAM X32 Ballout usi<span class="ls21">ng MO-XXX<span class="_ _3"> </span>.......<span class="ls1f">........<span class="_ _1"></span><span class="ls22">.........<span class="ls1c">...........<span class="_ _1"></span>...........</span></span></span></span></div><div class="t m0 x31 h11 y5b ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>.............<span class="_ _1"></span>..........<span class="_ _1"></span>..............<span class="_ _1"></span>....<span class="_ _4"></span>4</div><div class="t m0 x2d h11 y5c ff4 fsb fc0 sc0 ls26 ws0">2.7 <span class="_ _5"> </span>Pinout Description<span class="_ _6"></span>...............<span class="_ _1"></span>.................<span class="_ _1"></span>.........<span class="ls1c">.....<span class="_ _1"></span>.................<span class="_ _1"></span>..</span></div><div class="t m0 x32 h11 y5d ff4 fsb fc0 sc0 ls1c ws0">............<span class="_ _1"></span>................<span class="_ _1"></span>...........<span class="_ _1"></span>............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..........<span class="_ _4"></span>6</div><div class="t m0 x2d h11 y5e ff4 fsb fc0 sc0 ls20 ws0">2.8 <span class="_ _5"> </span>DDR4 SDRAM <span class="_ _1"></span>Addressing.....<span class="lse">.................................<span class="ls1c">...<span class="_ _1"></span>..............<span class="_ _1"></span>.........</span></span></div><div class="t m0 x2e h11 y5f ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>.........<span class="_ _1"></span>.............<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="_ _4"></span>7</div><div class="t m0 x2d h11 y60 ff4 fsb fc0 sc0 lse ws0">2.9 <span class="_ _5"> </span>DDP Single Rank(<span class="_ _1"></span>SR) x16 from two x8<span class="_ _7"> </span>................<span class="_ _1"></span>........<span class="ls1c">......<span class="_ _1"></span>..............<span class="_ _1"></span>.....</span></div><div class="t m0 x30 h11 y61 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..........<span class="_ _1"></span>.............<span class="_ _1"></span>..............<span class="_ _1"></span>.......<span class="_ _4"></span>9</div><div class="t m0 x2d h10 y62 ff5 fsb fc0 sc0 ls27 ws0">3<span class="_ _2"> </span>Functional Descrip<span class="_ _1"></span>tion <span class="_ _8"> </span>............<span class="_ _1"></span>.................<span class="_ _1"></span>..........<span class="_ _1"></span><span class="ls1c">.............<span class="_ _1"></span>..............<span class="_ _1"></span>................<span class="_ _1"></span>..............<span class="_ _1"></span>......<span class="ls28">......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>11</span></span></div><div class="t m0 x2d h11 y63 ff4 fsb fc0 sc0 ls18 ws0">3.1 <span class="_ _5"> </span>Simplified State Diagram <span class="_ _1"></span> ...............<span class="_ _1"></span>................<span class="_ _1"></span><span class="ls1c">............<span class="_ _1"></span>...........</span></div><div class="t m0 x33 h11 y64 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>............<span class="_ _1"></span>...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _9"> </span>1<span class="_ _a"></span>1</div><div class="t m0 x2d h11 y65 ff4 fsb fc0 sc0 ls1d ws0">3.2 <span class="_ _5"> </span>Basic Functionality<span class="_ _8"> </span>......<span class="ls29">.........................<span class="ls2a">.........<span class="ls1c">.............<span class="_ _1"></span>...........</span></span></span></div><div class="t m0 x32 h11 y66 ff4 fsb fc0 sc0 ls1c ws0">............<span class="_ _1"></span>................<span class="_ _1"></span>...........<span class="ls28">.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>12</span></div><div class="t m0 x2d h11 y67 ff4 fsb fc0 sc0 ls24 ws0">3.3 <span class="_ _5"> </span>RESET and Initialization <span class="ls2">Procedure<span class="_ _4"></span>........<span class="lse">...........<span class="ls25">......<span class="ls1c">.....<span class="_ _1"></span>.................</span></span></span></span></div><div class="t m0 x2f h11 y68 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>.............<span class="_ _1"></span><span class="ls27">...............<span class="_ _1"></span>.................<span class="_ _1"></span>.....<span class="_ _4"></span>12</span></div><div class="t m0 x2d h11 y69 ff4 fsb fc0 sc0 ls20 ws0">3.3.1 Power-up Initialization <span class="ls25">Se<span class="_ _4"></span>quence <span class="_ _6"></span>.........<span class="ls1f">........<span class="ls2">.......<span class="ls1c">..........<span class="_ _1"></span>.....</span></span></span></span></div><div class="t m0 x32 h11 y6a ff4 fsb fc0 sc0 ls1c ws0">............<span class="_ _1"></span>................<span class="_ _1"></span>..............<span class="_ _1"></span>......<span class="ls28">......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>12</span></div><div class="t m0 x2d h11 y6b ff4 fsb fc0 sc0 ls16 ws0">3.3.2 VDD Slew rate <span class="ls2b">at Power-u<span class="_ _4"></span>p Initialization Sequence <span class="_"> </span>.......<span class="ls1c">......<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span><span class="ls27">................<span class="_ _1"></span>...........<span class="_ _4"></span>13</span></span></span></div><div class="t m0 x2d h11 y6c ff4 fsb fc0 sc0 ls23 ws0">3.3.3 Reset Initialization with <span class="ls18">Stable Power <span class="_ _3"> </span>..................<span class="ls1c">...<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="ls28">..........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _4"></span>14</span></span></span></div><div class="t m0 x2d h11 y6d ff4 fsb fc0 sc0 ls2c ws0">3.4 <span class="_ _5"> </span>Register Definition<span class="_ _4"></span>....<span class="_ _1"></span>.................<span class="_ _1"></span>................<span class="_ _1"></span>...<span class="ls1c">.........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>................<span class="_ _1"></span>..........<span class="ls28">..<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>14</span></span></div><div class="t m0 x2d h11 y6e ff4 fsb fc0 sc0 lsb ws0">3.4.1 Programming the mode registers <span class="_ _6"></span>.......................<span class="_ _1"></span>...<span class="ls1c">.....<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="_ _1"></span><span class="ls27">...............<span class="_ _1"></span>.................<span class="_ _1"></span>.....<span class="_ _4"></span>14</span></span></div><div class="t m0 x2d h11 y6f ff4 fsb fc0 sc0 ls6 ws0">3.5 <span class="_ _5"> </span>Mode Register<span class="_ _4"></span>.............<span class="lse">.................................<span class="ls1c">...<span class="_ _1"></span>.................<span class="_ _1"></span>.....</span></span></div><div class="t m0 x32 h11 y70 ff4 fsb fc0 sc0 ls1c ws0">............<span class="_ _1"></span>................<span class="_ _1"></span>..........<span class="ls28">..<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>17</span></div><div class="t m0 x2d h10 y71 ff5 fsb fc0 sc0 ls2d ws0">4 <span class="_ _b"> </span>DDR4 SDRAM Command Description<span class="ls24"> and Opera<span class="_ _4"></span>tion<span class="ls2"> <span class="_ _3"> </span>................<span class="ls1c">...........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..........<span class="ls2c">....<span class="_ _1"></span>........<span class="_ _4"></span>28</span></span></span></span></div><div class="t m0 x2d h11 y72 ff4 fsb fc0 sc0 ls18 ws0">4.1 <span class="_ _5"> </span>Command T<span class="_ _a"></span>ruth T<span class="_ _c"></span>able<span class="_ _4"></span>..........................<span class="_ _1"></span>..............<span class="_ _1"></span><span class="ls1c">..............<span class="_ _1"></span>...........</span></div><div class="t m0 x34 h11 y73 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..........<span class="ls28">.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _4"></span>28</span></div><div class="t m0 x2d h11 y74 ff4 fsb fc0 sc0 ls18 ws0">4.2 <span class="_ _5"> </span>CKE T<span class="_ _a"></span>ruth T<span class="_ _c"></span>able<span class="_ _9"> </span>............<span class="_ _1"></span>.................<span class="_ _1"></span>...............<span class="_ _1"></span><span class="ls1c">................<span class="_ _1"></span>........</span></div><div class="t m0 x32 h11 y75 ff4 fsb fc0 sc0 ls1c ws0">............<span class="_ _1"></span>................<span class="_ _1"></span>...........<span class="ls28">.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>29</span></div><div class="t m0 x2d h11 y76 ff4 fsb fc0 sc0 ls2e ws0">4.3 <span class="_ _5"> </span>Burst Length, T<span class="_ _a"></span>ype and Order<span class="_ _4"></span>...........<span class="_ _1"></span>.................<span class="_ _1"></span>...<span class="ls1c">........<span class="_ _1"></span>.................</span></div><div class="t m0 x2f h11 y77 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..........<span class="ls28">.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _4"></span>30</span></div><div class="t m0 x2d h11 y78 ff4 fsb fc0 sc0 ls2f ws0">4.3.1 BL8 Burst order with CRC <span class="_ _1"></span>Enabled <span class="_ _4"></span>......................<span class="_ _1"></span>..<span class="ls1c">.......<span class="_ _1"></span>.................</span></div><div class="t m0 x2e h11 y79 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>...........<span class="_ _1"></span><span class="ls27">..............<span class="_ _1"></span>.................<span class="_ _1"></span>.....<span class="_ _4"></span>30</span></div><div class="t m0 x2d h11 y7a ff4 fsb fc0 sc0 ls30 ws0">4.4 <span class="_ _5"> </span>DLL-off Mode & DLL<span class="_ _1"></span> on/off<span class="ls1f"> Switching procedure<span class="_ _9"></span>.............<span class="_ _1"></span><span class="ls1c">.......</span></span></div><div class="t m0 x33 h11 y7b ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span><span class="ls27">..............<span class="_ _1"></span>..............<span class="_ _4"></span>31</span></div><div class="t m0 x2d h11 y7c ff4 fsb fc0 sc0 lsb ws0">4.4.1 DLL on/off switching procedure <span class="_ _4"></span>.........<span class="_ _1"></span>.................<span class="_ _1"></span><span class="ls1c">........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..........<span class="ls28">.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _4"></span>31</span></span></div><div class="t m0 x2d h11 y7d ff4 fsb fc0 sc0 ls31 ws0">4.4.2 DLL “on” to DLL “off” Procedure <span class="_ _4"></span>...................<span class="_ _1"></span>......<span class="_ _1"></span><span class="ls1c">..............<span class="_ _1"></span>................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="ls28">.......<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>31</span></span></div><div class="t m0 x2d h11 y7e ff4 fsb fc0 sc0 ls25 ws0">4.4.3 DLL “off” to DLL “on” P<span class="ls2c">rocedure <span class="_ _4"></span>................<span class="_ _1"></span>.........<span class="ls1c">..<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="ls28">.........<span class="_ _1"></span>...............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="_ _4"></span>32</span></span></span></div><div class="t m0 x2d h11 y7f ff4 fsb fc0 sc0 ls32 ws0">4.5 <span class="_ _5"> </span>DLL-of<span class="_ _1"></span>f Mode<span class="_ _7"> </span>........<span class="_ _1"></span>.................<span class="_ _1"></span>.................<span class="_ _1"></span>.....<span class="ls1c">...<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="ls28">..........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _4"></span>33</span></span></div><div class="t m0 x2d h11 y80 ff4 fsb fc0 sc0 lsb ws0">4.6 <span class="_ _5"> </span>Input Clock Frequency Change<span class="_"> </span>.....<span class="_ _1"></span>....................<span class="_ _1"></span>......<span class="ls1c">.....<span class="_ _1"></span>..............<span class="_ _1"></span>......</span></div><div class="t m0 x2e h11 y81 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>..........<span class="ls27">.<span class="_ _1"></span>.................<span class="_ _1"></span>.................<span class="_ _1"></span>..<span class="_ _4"></span>34</span></div><div class="t m0 x2d h11 y82 ff4 fsb fc0 sc0 ls33 ws0">4.7 <span class="_ _5"> </span>Wr<span class="_ _1"></span>ite Leveling<span class="_ _3"> </span>........................<span class="_ _1"></span>.................<span class="_ _1"></span>....<span class="ls1c">.<span class="_ _1"></span>.................<span class="_ _1"></span>......</span></div><div class="t m0 x35 h11 y83 ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>...........<span class="_ _1"></span><span class="ls28">..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _4"></span>35</span></div><div class="t m0 x2d h11 y84 ff4 fsb fc0 sc0 ls1d ws0">4.7.1 DRAM setting for write lev<span class="ls20">eling & DRAM termina<span class="_ _4"></span>tion functi<span class="ls34">on in that mode <span class="_ _9"></span>.....<span class="_ _1"></span>.................<span class="_ _1"></span>.................<span class="_ _1"></span>........<span class="_ _1"></span>..............<span class="_ _4"></span>36</span></span></div><div class="t m0 x2d h11 y85 ff4 fsb fc0 sc0 ls20 ws0">4.7.2 Procedure Description<span class="_ _6"></span>.<span class="ls29">..............<span class="ls1f">............<span class="ls2a">.........<span class="ls1c">..<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="ls28">.........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>36</span></span></span></span></span></div><div class="t m0 x2d h11 y86 ff4 fsb fc0 sc0 ls18 ws0">4.7.3 Write Leveling Mode Exit...<span class="_ _1"></span>.................<span class="_ _1"></span>.............<span class="_ _1"></span><span class="ls1c">............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>......<span class="ls28">.....<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _4"></span>37</span></span></div><div class="t m0 x2d h11 y87 ff4 fsb fc0 sc0 ls26 ws0">4.8 <span class="_ _5"> </span>T<span class="_ _c"></span>emperature controlled Refr<span class="_ _1"></span>esh modes<span class="_ _6"></span>.......................<span class="_ _1"></span><span class="ls1c">.........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>............<span class="_ _1"></span><span class="ls27">.................<span class="_ _1"></span>................<span class="_ _4"></span>38</span></span></div><div class="t m0 x2d h11 y88 ff4 fsb fc0 sc0 ls1e ws0">4.8.1 Normal temperat<span class="ls25">ure mode ( 0°C =< TC<span class="ls35">ASE =< 85°C ) <span class="_"> </span>........<span class="ls1c">...<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="ls33">.............<span class="_ _1"></span>........<span class="_ _4"></span>38</span></span></span></span></div><div class="t m0 x2d h11 y89 ff4 fsb fc0 sc0 ls36 ws0">4.8.2 Extended temper<span class="ls37">ature mode ( 0<span class="ls21">°C =< TCASE =< 95°C ) <span class="_ _4"></span>......<span class="ls1c">................<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="ls38">............<span class="_ _1"></span>........<span class="_ _4"></span>38</span></span></span></span></div><div class="t m0 x2d h11 y8a ff4 fsb fc0 sc0 ls31 ws0">4.9 <span class="_ _5"> </span>Fine Granularity Refresh Mode<span class="_ _6"></span>.............................<span class="_ _1"></span>.<span class="ls1c">..........<span class="_ _1"></span>..............</span></div><div class="t m0 x2f h11 y8b ff4 fsb fc0 sc0 ls1c ws0">...........<span class="_ _1"></span>.................<span class="_ _1"></span>...........<span class="_ _1"></span><span class="ls28">..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _4"></span>39</span></div><div class="t m0 x2d h11 y8c ff4 fsb fc0 sc0 ls39 ws0">4.9.1 Mode Register and Comm<span class="_ _4"></span><span class="ls18">and Truth <span class="_ _1"></span>Table<span class="_ _9"></span>......<span class="_ _1"></span>.....</span></div><div class="t m0 x23 h11 y8d ff4 fsb fc0 sc0 ls18 ws0">.........<span class="ls1c">...<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>................<span class="_ _1"></span>..<span class="ls27">.............<span class="_ _1"></span>................<span class="_ _4"></span>39</span></span></div><div class="t m0 x2d h11 y8e ff4 fsb fc0 sc0 ls2c ws0">4.9.2 tREFI and tRFC paramet<span class="_ _1"></span>ers...............<span class="_ _1"></span>.................<span class="_ _1"></span><span class="ls1c">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="_ _1"></span><span class="ls28">............<span class="_ _1"></span>.................<span class="_ _1"></span>...........<span class="_ _4"></span>40</span></span></div><div class="t m0 x2d h11 y8f ff4 fsb fc0 sc0 ls2e ws0">4.9.3 Changing Refresh Rate<span class="_ _4"></span>........<span class="_ _1"></span>.................<span class="_ _1"></span>...........<span class="ls1c">...<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>....<span class="ls28">..........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>40</span></span></div><div class="t m0 x2d h11 y90 ff4 fsb fc0 sc0 ls1d ws0">4.9.4 Usage with Temper<span class="ls3a">ature Controlle<span class="_ _4"></span>d Refresh mode<span class="_ _9"></span>...........<span class="ls1c">..........<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="ls33">...<span class="_ _1"></span>.................<span class="_ _1"></span>.....<span class="_ _4"></span>41</span></span></span></div><div class="t m0 x2d h11 y91 ff4 fsb fc0 sc0 ls2c ws0">4.9.5 Self Refres<span class="_ _1"></span>h entry and exit<span class="_ _6"></span>.........................<span class="_ _1"></span>.....<span class="ls1c">....<span class="_ _1"></span>..............<span class="_ _1"></span>................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="ls28">...........<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..<span class="_ _4"></span>41</span></span></div><div class="t m0 x2d h11 y92 ff4 fsb fc0 sc0 ls37 ws0">4.10 Multi Purpose Register<span class="_ _6"></span>........................<span class="_ _1"></span>............<span class="ls1c">..<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="ls28">.........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>........<span class="_ _4"></span>41</span></span></div><div class="t m0 x2d h11 y93 ff4 fsb fc0 sc0 ls37 ws0">4.10.1 DQ Training with MPR...........<span class="_ _1"></span>................<span class="_ _1"></span>.........<span class="ls1c">...<span class="_ _1"></span>................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..<span class="ls28">..........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>41</span></span></div><div class="t m0 x2d h11 y94 ff4 fsb fc0 sc0 ls26 ws0">4.10.2 MR3 definition <span class="_ _3"> </span>................<span class="_ _1"></span>.................<span class="_ _1"></span>........<span class="_ _1"></span><span class="ls1c">..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>....<span class="ls28">.......<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>...........<span class="_ _4"></span>41</span></span></div><div class="t m0 x2d h11 y95 ff4 fsb fc0 sc0 ls25 ws0">4.10.3 MPR Reads <span class="_ _9"></span>..............<span class="_ _1"></span><span class="ls1f">............<span class="lse">...........<span class="ls2a">.........<span class="ls1c">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="ls28">.<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.....<span class="_ _4"></span>42</span></span></span></span></span></div><div class="t m0 x2d h11 y96 ff4 fsb fc0 sc0 ls34 ws0">4.10.4 MPR Writes <span class="_ _9"> </span>..........................<span class="_ _1"></span>................<span class="_ _1"></span>...<span class="ls1c">...<span class="_ _1"></span>..............<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="ls28">..........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>...........<span class="_ _4"></span>44</span></span></div><div class="t m0 x2d h11 y97 ff4 fsb fc0 sc0 ls25 ws0">4.10.5 MPR Read Data format <span class="_ _9"></span>..<span class="_ _1"></span><span class="lse">.................................<span class="ls1c">...<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.<span class="ls28">..........<span class="_ _1"></span>.................<span class="_ _1"></span>..............<span class="_ _4"></span>47</span></span></span></div><div class="t m0 x2d h11 y98 ff4 fsb fc0 sc0 ls24 ws0">4.1<span class="_ _a"></span>1 Data Mask(DM), Data Bus Inve<span class="lsb">rsion (DBI) and T<span class="_ _1"></span>DQS<span class="_ _4"></span>....</span></div><div class="t m0 x36 h11 y99 ff4 fsb fc0 sc0 lsb ws0">......<span class="ls1c">........<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>..............<span class="_ _1"></span>.............<span class="_ _1"></span><span class="ls33">...............<span class="_ _1"></span>........<span class="_ _4"></span>52</span></span></div><div class="t m0 x37 h12 y9a ff5 fs4 fc0 sc0 ls3b ws0">DDR4 SDRAM ST<span class="_ _c"></span>ANDARD</div><div class="t m0 x38 h12 y9b ff5 fs4 fc0 sc0 ls2 ws0">Contents</div><div class="t m0 x3 hb y1b ff3 fs7 fc1 sc0 ls2 ws0"><span class="fc2 sc0">Downloaded by ?? ? (zhenlong.yan@keysight.com) on Jul 29, 2019, 7:34 pm PDT</span></div><div class="t m1 x4 hc y1c ff3 fs8 fc1 sc0 ls2 ws0"><span class="fc2 sc0">keysight</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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