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<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596585/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596585/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">7<span class="_"> </span>Series FPGAs </div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">Configurable Logic Block</div><div class="t m0 x1 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">User Guide</div><div class="t m0 x1 h4 y4 ff1 fs2 fc0 sc0 ls3 ws3">UG474 (v1.8) Sept<span class="_ _0"></span>ember 27, 2016</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596585/bg2.jpg"><div class="t m0 x2 h5 y5 ff1 fs3 fc0 sc0 ls4 ws4">7<span class="_"> </span>Series FPGAs CLB User Guide<span class="_ _1"> </span><span class="ff3 fc1 ls5 ws5">www.xilinx.com<span class="_ _2"> </span><span class="fc0 ls6 ws6">UG474 (v1.8) S<span class="ls7 ws7">eptember 27<span class="_ _3"></span>, 2016</span></span></span></div><div class="t m0 x2 h6 y6 ff1 fs4 fc0 sc0 ls8 ws5">DISCLAIMER</div><div class="t m0 x2 h7 y7 ff4 fs5 fc0 sc0 ls9 ws8">The information disc<span class="_ _3"></span>losed to you hereu<span class="_ _3"></span>nder (the “Materials<span class="_ _3"></span>”) is pr<span class="lsa ws9">ovided solely<span class="_ _3"></span> for the selection and use of Xil<span class="_ _3"></span>inx products. T<span class="lsb wsa">o the maximum </span></span></div><div class="t m0 x2 h7 y8 ff4 fs5 fc0 sc0 lsc wsb">extent permitted by applicable law: (1) Materials<span class="_ _0"></span> are made avai<span class="_ _0"></span><span class="lsd wsc">lable “AS IS” and with all faults, Xilinx hereby DISCLAI<span class="_ _3"></span>MS ALL W<span class="lse ws5">ARRANTIES </span></span></div><div class="t m0 x2 h7 y9 ff4 fs5 fc0 sc0 lsf wsd">AND CONDITIONS, EXP<span class="_ _0"></span>RESS, IMPLIED, OR STATUTO<span class="_ _0"></span>RY, INCLUDING BUT NOT LIM<span class="_ _0"></span>ITED TO WARRANTIES OF MERCH<span class="_ _0"></span>ANTABILITY, NON-</div><div class="t m0 x2 h7 ya ff4 fs5 fc0 sc0 lsf wse">INFRINGEMENT, O<span class="_ _0"></span>R FITNESS FOR AN<span class="_ _0"></span>Y PARTICULAR PU<span class="_ _0"></span>RPOSE; and (<span class="_ _0"></span>2) Xilinx sh<span class="_ _0"></span>all not be<span class="_ _0"></span> liable (wheth<span class="_ _0"></span>er in contra<span class="_ _0"></span>ct or tort, incl<span class="_ _0"></span>uding<span class="_ _0"></span><span class="ls8 ws5"> </span></div><div class="t m0 x2 h7 yb ff4 fs5 fc0 sc0 ls10 wsf">negligence, or under any<span class="_ _3"></span> other theory of liabil<span class="_ _3"></span>ity) for any loss <span class="_ _3"></span><span class="ls11 ws10">or damage of any kind<span class="_ _0"></span> or nature rela<span class="_ _0"></span>ted to, arisin<span class="_ _0"></span>g under, or <span class="ls12 ws11">in connection with, </span></span></div><div class="t m0 x2 h7 yc ff4 fs5 fc0 sc0 ls13 wse">the Materials (<span class="_ _0"></span>including you<span class="_ _0"></span>r use of the <span class="_ _0"></span>Materials), in<span class="_ _0"></span>cluding for <span class="_ _0"></span>any direct, i<span class="_ _0"></span>ndirect, spec<span class="_ _0"></span>ial, inciden<span class="_ _0"></span>tal, or conse<span class="_ _0"></span>quential <span class="_ _0"></span><span class="ls14 ws12">loss or dama<span class="_ _3"></span>ge </span></div><div class="t m0 x2 h7 yd ff4 fs5 fc0 sc0 ls15 ws13">(including loss of data, profits, goodwill, or<span class="ls16 ws14"> any type of loss or damage<span class="ls17 ws15"> suffered as a result of an<span class="ls18 ws16">y action brought by a third<span class="ls14 ws17"> party) e<span class="_ _3"></span>ven if such </span></span></span></span></div><div class="t m0 x2 h7 ye ff4 fs5 fc0 sc0 ls19 ws18">damage or loss was reasonably foreseeable or Xilinx had been ad<span class="ls1a ws19">vi<span class="_ _0"></span>sed of the possibility<span class="_ _0"></span> of the same. Xilinx assumes no oblig<span class="_ _0"></span>ati<span class="ls1b ws1a">on to correct </span></span></div><div class="t m0 x2 h7 yf ff4 fs5 fc0 sc0 ls10 ws1b">any errors contained in the Materials or to notify you of upda<span class="ls1c ws1c">tes to the Materials or to prod<span class="_ _3"></span><span class="ls1d ws1d">uct specifications<span class="_ _3"></span>. You may not <span class="_ _3"></span>re<span class="ls1e ws5">produce, </span></span></span></div><div class="t m0 x2 h7 y10 ff4 fs5 fc0 sc0 ls1e ws1e">modify, distribute, or publicly disp<span class="_ _3"></span>lay the Materials without pr<span class="lsd ws1f">ior writte<span class="_ _3"></span>n consent. Certain pr<span class="_ _3"></span>od<span class="ls18 ws20">ucts are subject to the terms <span class="ls9 ws21">and c<span class="_ _3"></span>onditions </span></span></span></div><div class="t m0 x2 h7 y11 ff4 fs5 fc0 sc0 ls12 ws11">of Xilinx’s limited warran<span class="_ _3"></span>ty, please refer to Xilinx’s Terms of <span class="_ _3"></span><span class="ls1f ws22">Sale which can be viewed at <span class="fc1 lsa ws5">http://www.x<span class="_ _3"></span>ilinx.com/legal.htm#tos</span></span></div><div class="t m0 x3 h7 y12 ff4 fs5 fc0 sc0 ls20 ws23">; IP cores may be </div><div class="t m0 x2 h7 y13 ff4 fs5 fc0 sc0 ls21 ws24">subject to warran<span class="_ _3"></span>ty and support <span class="_ _3"></span>terms cont<span class="_ _3"></span>ained in a <span class="_ _3"></span>license issu<span class="_ _3"></span><span class="ls22 ws25">ed to you by <span class="_ _3"></span>Xilinx. Xilinx p<span class="_ _3"></span>roducts are not <span class="_ _3"></span>designed or<span class="_ _3"></span> inten<span class="ws26">ded to be <span class="_ _3"></span>fail-</span></span></div><div class="t m0 x2 h7 y14 ff4 fs5 fc0 sc0 ls9 ws27">safe or for use in any application requirin<span class="lsf ws28">g fail-safe performance; you assume s<span class="_ _0"></span>ole ri<span class="ls9 ws27">sk and liability for use of Xilinx produc<span class="ls23 ws29">ts in such critical </span></span></span></div><div class="t m0 x2 h7 y15 ff4 fs5 fc0 sc0 ls23 ws2a">applications, ple<span class="_ _0"></span>ase refer to Xilinx<span class="_ _0"></span>’s Terms of Sale whic<span class="_ _0"></span>h can be viewed at <span class="fc1 ls10 ws5">http://www.xilinx.com/legal.htm#tos</span></div><div class="t m0 x4 h7 y16 ff4 fs5 fc0 sc0 ls8 ws5">.</div><div class="t m0 x2 h8 y17 ff5 fs5 fc0 sc0 lsc ws2b">Automotive Applications Disclaimer</div><div class="t m0 x2 h7 y18 ff4 fs5 fc0 sc0 ls17 ws2c">AUTOMOTIVE PRODUCTS (IDENTIFIED AS "XA" IN THE PAR<span class="_ _0"></span>T NUMB<span class="lsf ws28">ER) ARE NOT WARRANT<span class="_ _0"></span>ED FOR USE IN THE DEPLOY<span class="_ _0"></span>MENT OF AIRBAGS </span></div><div class="t m0 x2 h7 y19 ff4 fs5 fc0 sc0 ls24 ws2d">OR FOR USE IN APPLIC<span class="_ _0"></span>ATIONS TH<span class="ls25 ws2e">AT AFFECT CONTROL OF A <span class="_ _0"></span>VEHICLE ("SAFETY APPL<span class="lsf ws2f">ICATION")<span class="_ _0"></span> UNLESS THERE<span class="_ _0"></span> IS<span class="ls26 ws30"> A SAFETY CONCEPT OR </span></span></span></div><div class="t m0 x2 h7 y1a ff4 fs5 fc0 sc0 ls19 ws31">REDUNDANCY FEATURE CONSISTENT WIT<span class="_ _0"></span>H TH<span class="ls17 ws32">E ISO 26262 AU<span class="_ _0"></span>TOMOTIVE SAFETY STANDARD <span class="_ _0"></span>("SAFETY DESIGN"). CUS<span class="_ _0"></span>TOMER SHALL, </span></div><div class="t m0 x2 h7 y1b ff4 fs5 fc0 sc0 lse ws33">PRIOR TO USING OR DISTRIBUT<span class="_ _0"></span>ING ANY SYSTEMS THAT INCORPOR<span class="_ _0"></span><span class="ls27 ws34">ATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY </span></div><div class="t m0 x2 h7 y1c ff4 fs5 fc0 sc0 lsc ws35">PURPOSES. USE OF PRODUCTS IN<span class="_ _0"></span> A SAFETY APPLICATION WITHOUT <span class="_ _0"></span>A SA<span class="ls28 ws36">FETY DESIGN IS FULL<span class="ls13 ws37">Y AT THE RIS<span class="_ _0"></span>K OF CUSTOMER, SUBJECT<span class="_ _0"></span> ONLY </span></span></div><div class="t m0 x2 h7 y1d ff4 fs5 fc0 sc0 lsc wsb">TO APPLICABLE LAWS AND REGUL<span class="_ _0"></span>ATIONS GOVE<span class="ls29 ws38">RNING LIMITATION<span class="_ _0"></span>S ON PRODUCT LIABILITY.</span></div><div class="t m0 x2 h7 y1e ff4 fs5 fc0 sc0 ls12 ws39">© Copyright 2011–2016 Xilinx, Inc. Xilinx, the Xilinx logo, Arti<span class="_ _3"></span>x,<span class="ls2a ws3a"> ISE, Kintex, Spartan, Virtex, <span class="_ _3"></span>Vivado, Zynq, and other design<span class="ls2b ws3b">at<span class="_ _3"></span>ed br<span class="_ _3"></span>ands </span></span></div><div class="t m0 x2 h7 y1f ff4 fs5 fc0 sc0 ls9 ws3c">included herein are tradem<span class="ls11 ws3d">arks of Xilinx in<span class="_ _0"></span> the Unite<span class="_ _0"></span>d Stat<span class="lsd wsc">es and other countries. All other tr<span class="ls1e ws3e">ademarks are the pr<span class="_ _3"></span>operty of the<span class="ls9 ws21">ir respective </span></span></span></span></div><div class="t m0 x2 h7 y20 ff4 fs5 fc0 sc0 ls2c ws5">owners.</div><div class="t m0 x2 h9 y21 ff1 fs6 fc0 sc0 ls2d ws3f">Revision History</div><div class="t m0 x2 ha y22 ff6 fs2 fc0 sc0 ls2e ws40">The following table shows the revision history for this document.</div><div class="t m0 x5 hb y23 ff1 fs7 fc0 sc0 ls2f ws5">Date<span class="_ _4"> </span>Version<span class="_ _5"> </span>Revision</div><div class="t m0 x6 hc y24 ff6 fs7 fc0 sc0 ls30 ws41">03/01/2011<span class="_ _6"> </span>1.0<span class="_ _7"> </span>Xilinx Initial release.</div><div class="t m0 x6 hc y25 ff6 fs7 fc0 sc0 ls8 ws41">03/28/2011<span class="_ _6"> </span>1.1<span class="_ _7"> </span>Added devices XC7K355T, XC7K420T, and XC7K480T to <span class="fc1 ls31 ws5">Table<span class="_"> </span>1-3</span><span class="ls32 ws42">. Portions of the text </span></div><div class="t m0 x7 hc y26 ff6 fs7 fc0 sc0 ls31 ws43">have been revised for clarity.</div><div class="t m0 x6 hc y27 ff6 fs7 fc0 sc0 ls31 ws43">09/30/2011<span class="_ _6"> </span>1.2<span class="_ _7"> </span>Added last sentence under <span class="fc1 ls33 ws44">7 Series CLB Features</span><span class="ls34 ws45">. Added <span class="fc1 ls35 ws5">Table<span class="_"> </span>1-3</span><span class="ls36 ws46"> and <span class="fc1 ls35 ws5">Table<span class="_"> </span>1-4<span class="fc0 ls37">. </span></span></span></span></div><div class="t m0 x7 hc y28 ff6 fs7 fc0 sc0 ls38 ws47">Updated CLB features in <span class="fc1 ls35 ws5">Table<span class="_"> </span>1<span class="_ _0"></span>-3<span class="fc0 ls39 ws48">. Added first<span class="_ _0"></span> sentence under <span class="fc1 ls3a ws49">CLB<span class="_ _0"></span> Arrangement<span class="fc0 ls37 ws5">, </span></span></span></span></div><div class="t m0 x7 hc y29 ff6 fs7 fc0 sc0 ls32 ws5">added <span class="fc1 ls31 ws4a">ASMBL Architecture</span><span class="ls3b ws4b"> section, and <span class="fc1 ls3c ws4c">CLB Slices</span><span class="ls3d ws4d"> heading. Added <span class="_ _3"></span>last paragraph </span></span></div><div class="t m0 x7 hc y2a ff6 fs7 fc0 sc0 ls3e ws5">under <span class="fc1 ls2f ws4e">Carry Logic<span class="fc0 ls3d">. Added lasts sentence under </span><span class="ws4f">Using Carry Logic</span></span><span class="ls3f ws50">. Added second </span></div><div class="t m0 x7 hc y2b ff6 fs7 fc0 sc0 ls3a ws51">sentence under <span class="fc1 ls31 ws52">Slice Multiplexer Timing Parameters</span><span class="ls37 ws53">. Modified <span class="fc1 ls35 ws5">Table<span class="_"> </span>5-2</span><span class="ws5">, <span class="fc1 ls35">Table<span class="_ _8"> </span>5-4</span><span class="ls40 ws54">, and </span></span></span></div><div class="t m0 x7 hc y2c ff6 fs7 fc1 sc0 ls41 ws5">Table<span class="_"> </span>5-5<span class="fc0 ls42 ws55"> for clarity. Added </span><span class="ws56">Devices Using Stacked Silicon <span class="ls3d ws57">Interconnect (SSI) Technology</span></span><span class="fc0 ls8"> </span></div><div class="t m0 x7 hc y2d ff6 fs7 fc0 sc0 ls3d ws5">section.</div><div class="t m0 x6 hc y2e ff6 fs7 fc0 sc0 ls30 ws5">01/30/2012<span class="_ _6"> </span>1.3<span class="_ _7"> </span>Revised <span class="_ _9"></span><span class="fc1 ls35">Table<span class="_"> </span>1-2<span class="fc0 ls3a ws58">. Added fifth paragraph under </span><span class="ls3d ws57">Distributed RAM (Available in SLICEM </span></span></div><div class="t m0 x7 hc y2f ff6 fs7 fc1 sc0 ls30 ws5">Only)<span class="fc0 ls2f ws4e">. Clarified last paragraph under </span><span class="ls43 ws59">Global Controls GSR and GTS</span><span class="fc0 ls8">.</span></div><div class="t m0 x6 hc y30 ff6 fs7 fc0 sc0 ls43 ws5a">11/05/2012<span class="_ _6"> </span>1.4<span class="_ _7"> </span>Changed “unifo<span class="ws5b">rmity” to “optimized” in last bullet under <span class="fc1 ls33 ws44">7 Series CLB Features</span><span class="ls37 ws5">. </span></span></div><div class="t m0 x7 hc y31 ff6 fs7 fc0 sc0 ls8 ws5c">Changed “unified” to “scalable<span class="ls3c ws4c">” in first sentence under <span class="fc1 ls3e ws5d">D<span class="_ _3"></span>evice Resources</span><span class="ls44 ws5e">. Deleted </span></span></div><div class="t m0 x7 hc y32 ff6 fs7 fc0 sc0 ls3d ws5b">7A350T device from <span class="fc1 ls35 ws5">Table<span class="_"> </span>1-2</span><span class="ls43 ws59">. Deleted 7V1500T and 7VH290T devices from <span class="fc1 ls35 ws5">Table<span class="_ _8"> </span>1-4<span class="fc0 ls37">. </span></span></span></div><div class="t m0 x7 hc y33 ff6 fs7 fc0 sc0 ls41 ws5f">Added reference to 7 Series<span class="ls45 ws60"> FPGA Libraries Guide to <span class="fc1 ls46 ws61">Distributed RAM (Available in </span></span></div><div class="t m0 x7 hc y34 ff6 fs7 fc1 sc0 ls3d ws5b">SLICEM Only)<span class="fc0 ls47 ws5">, </span><span class="ls2f ws4e">Shift Registers (Available in SLICEM Only)<span class="fc0 ls48 ws62">, and </span><span class="ls45 ws63">Flip-Flop Primitives<span class="fc0 ls37 ws5">. </span></span></span></div><div class="t m0 x7 hc y35 ff6 fs7 fc0 sc0 ls45 ws63">Changed “T</div><div class="t m0 x8 hd y36 ff6 fs8 fc0 sc0 ls49 ws5">CEO</div><div class="t m0 x9 hc y37 ff6 fs7 fc0 sc0 ls3e ws5d">” to “T</div><div class="t m0 xa hd y36 ff6 fs8 fc0 sc0 ls49 ws5">CECK</div><div class="t m0 xb hc y37 ff6 fs7 fc0 sc0 ls30 ws41">” in <span class="fc1 ls3e ws5">Figure<span class="_"> </span>5-2</span><span class="ls4a ws64"> and first bullet under <span class="_ _0"></span><span class="fc1 ls4b ws65">General Timing </span></span></div><div class="t m0 x7 hc y38 ff6 fs7 fc1 sc0 ls4b ws5">Characteristics<span class="fc0 ls8">.</span></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596585/bg3.jpg"><div class="t m0 x2 h5 y5 ff3 fs3 fc0 sc0 ls4c ws66">UG474 (v1.8) September 27, 2016<span class="_ _2"> </span><span class="fc1 ws5">www.xilinx.com<span class="_ _1"> </span></span><span class="ff1 ls4d ws67">7<span class="_"> </span>Series<span class="_ _3"></span> FPGAs CLB <span class="_ _3"></span>User Guid<span class="_ _3"></span>e</span></div><div class="t m0 xc hc y39 ff6 fs7 fc0 sc0 ls31 ws4a">08/6/2013<span class="_ _a"> </span>1.5<span class="_ _7"> </span>Added Artix®-7 devices. Update<span class="ls30 ws41">d references to implementation tools.</span></div><div class="t m0 x6 he y3a ff6 fs7 fc0 sc0 ls43 ws68">08/11/2014<span class="_ _6"> </span>1.6 Revised <span class="_ _b"></span>footnotes <span class="_ _b"></span>in <span class="_ _b"></span><span class="fc1 ls31 ws5">Table<span class="_"> </span>1-2<span class="fc0 ws43"> through </span><span class="ls48">Table<span class="_"> </span>1-4<span class="fc0 ls35 ws69">. Revised polarity from <span class="ff7 ls41 ws5">independent</span><span class="ls4b ws65"> to </span></span></span></span></div><div class="t m0 x7 he y3b ff7 fs7 fc0 sc0 ls4e ws5">programmable<span class="ff6 ls46 ws6a"> in <span class="fc1 ls3d ws5b">Control Signals, page<span class="_"> </span>22</span><span class="ls2f ws4f">. Added Primitive column to <span class="_ _3"></span><span class="fc1 ls41 ws5">Table<span class="_"> </span>2-3</span><span class="ls31 ws43"> and </span></span></span></div><div class="t m0 x7 hc y3c ff6 fs7 fc0 sc0 ls33 ws6b">removed footnotes. Renamed<span class="_ _0"></span> or made minor revisions to <span class="fc1 ls4f ws5">Figure<span class="_"> </span>2-6</span><span class="ls31 ws6c"> through <span class="fc1 ls50 ws5">Figure<span class="_"> </span>2-14<span class="fc0 ls47">. </span></span></span></div><div class="t m0 x7 hc y3d ff6 fs7 fc0 sc0 ls30 ws6d">Revised sections <span class="fc1 ls31 ws6e">Clock – WCLK, page<span class="_ _c"> </span>49</span><span class="ls37 ws5">, <span class="fc1 ls51 ws6f">Clock – CLK, page<span class="_"> </span>50</span><span class="ls48 ws70">, and <span class="_ _3"></span><span class="fc1 ls8 ws5c">Clock - C, page<span class="_"> </span>51</span></span><span class="ls8">.</span></span></div><div class="t m0 x6 hc y3e ff6 fs7 fc0 sc0 ls4b ws71">11/17/2014<span class="_ _6"> </span>1.7 Updated <span class="_ _b"></span><span class="fc1 ls35 ws5">Table<span class="_"> </span>1-2<span class="fc0 ls2f ws4f"> for new Artix 7A15T device.</span></span></div><div class="t m0 x6 hc y3f ff6 fs7 fc0 sc0 ls2f ws4f">09/27/2016<span class="_ _6"> </span>1.8<span class="_ _7"> </span>Added Spartan®-7 device fa<span class="ls31 ws4a">mily (updated Preface and added <span class="fc1 ws5">Table<span class="_"> </span>1-1</span><span class="ls52 ws72">). Adde<span class="_ _3"></span>d </span></span></div><div class="t m0 x7 hc y40 ff6 fs7 fc0 sc0 ls2f ws4f">Artix®-7 7A12T and 7A25T devices to <span class="fc1 ls35 ws5">Table<span class="_"> </span>1-2<span class="fc0 ls8">.</span></span></div><div class="t m0 x5 hb y41 ff1 fs7 fc0 sc0 ls2f ws5">Date<span class="_ _4"> </span>Version<span class="_ _5"> </span>Revision</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596585/bg4.jpg"><div class="t m0 x2 h5 y5 ff1 fs3 fc0 sc0 ls4 ws4">7<span class="_"> </span>Series FPGAs CLB User Guide<span class="_ _1"> </span><span class="ff3 fc1 ls5 ws5">www.xilinx.com<span class="_ _2"> </span><span class="fc0 ls6 ws6">UG474 (v1.8) S<span class="ls7 ws7">eptember 27<span class="_ _3"></span>, 2016</span></span></span></div><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596585/bg5.jpg"><div class="t m0 x2 h5 y5 ff1 fs3 fc0 sc0 ls4 ws4">7<span class="_"> </span>Series FPGAs CLB User Guide<span class="_ _1"> </span><span class="ff3 fc1 ls5 ws5">www.xilinx.com<span class="_ _d"> </span></span><span class="ls8 ws5">5</span></div><div class="t m0 x2 h5 y42 ff3 fs3 fc0 sc0 ls4c ws66">UG474 (v1.8) September 27, 2016</div><div class="t m0 xd hf y43 ff8 fs9 fc0 sc0 ls53 ws73">Revision History<span class="ff6 fs2 ls54 ws5"> . . . . . . . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>.<span class="_ _8"> </span> 2</span></div><div class="t m0 xe h10 y44 ff1 fsa fc0 sc0 ls55 ws74">Preface: About This Guide</div><div class="t m0 xd hf y45 ff8 fs9 fc0 sc0 ls56 ws75">Guide Contents<span class="_ _e"></span><span class="ff6 fs2 ls54 ws5"> . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . .<span class="_ _8"> </span> 7</span></div><div class="t m0 xd hf y46 ff8 fs9 fc0 sc0 ls53 ws73">Additional Support Resources<span class="_ _e"></span><span class="ff6 fs2 ls54 ws5">. . . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>.<span class="_ _8"> </span> 8</span></div><div class="t m0 xe h10 y47 ff1 fsa fc0 sc0 ls57 ws76">Chapter<span class="_"> </span>1: Overview</div><div class="t m0 xd hf y48 ff8 fs9 fc0 sc0 ls53 ws77">CLB Overview<span class="_ _f"></span><span class="ff6 fs2 ls54 ws5"> . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . .<span class="_ _8"> </span> <span class="ls8">9</span></span></div><div class="t m0 xd hf y49 ff8 fs9 fc0 sc0 ls58 ws78">7 Series CLB Features<span class="_ _8"> </span><span class="ff6 fs2 ls59 ws79"> . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . .<span class="_ _8"> </span> 10</span></div><div class="t m0 xd hf y4a ff8 fs9 fc0 sc0 ls5a ws7a">Device Resources<span class="_ _8"> </span><span class="ff6 fs2 ls59 ws79"> . . . . . . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . .<span class="_ _8"> </span> 10</span></div><div class="t m0 xd hf y4b ff8 fs9 fc0 sc0 ls5b ws7b">Recommended Design Flow<span class="_ _f"></span><span class="ff6 fs2 ls59 ws79">. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> .<span class="_ _8"> </span> 12</span></div><div class="t m0 xd hf y4c ff8 fs9 fc0 sc0 ls5c ws7c">Pinout Planning<span class="_ _e"></span><span class="ff6 fs2 ls59 ws79">. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 13</span></div><div class="t m0 xe h10 y4d ff1 fsa fc0 sc0 ls5d ws7d">Chapter<span class="_"> </span>2: Functional Details</div><div class="t m0 xd hf y4e ff8 fs9 fc0 sc0 ls5e ws7e">CLB Arrangement<span class="_ _10"> </span><span class="ff6 fs2 ls59 ws79">. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 15</span></div><div class="t m0 xd hf y4f ff8 fs9 fc0 sc0 ls5f ws7f">Slice Description<span class="_ _10"> </span><span class="ff6 fs2 ls59 ws79">. . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> .<span class="_"> </span> 18</span></div><div class="t m0 xd hf y50 ff8 fs9 fc0 sc0 ls5b ws7b">Look-Up Table (LUT)<span class="_ _10"> </span><span class="ff6 fs2 ls59 ws79"> . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . .<span class="_ _8"> </span> 21</span></div><div class="t m0 xd hf y51 ff8 fs9 fc0 sc0 ls60 ws5">Storage Elements<span class="_ _e"></span><span class="ff6 fs2 ls59 ws79">. . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 21</span></div><div class="t m0 xd hf y52 ff8 fs9 fc0 sc0 ls5e ws7e">Distributed RAM (Available in SLICEM Only)<span class="ff6 fs2 ls61 ws80"> . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 23</span></div><div class="t m0 xd hf y53 ff8 fs9 fc0 sc0 ls62 ws81">Shift Registers (Available in SLICEM Only)<span class="_ _8"> </span><span class="ff6 fs2 ls59 ws79">. . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . .<span class="_ _8"> </span> 34</span></div><div class="t m0 xd hf y54 ff8 fs9 fc0 sc0 ls5f ws5">Multiplexers<span class="_ _e"></span><span class="ff6 fs2 ls54"> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . <span class="ls63 ws82">. 3<span class="_ _11"></span>9</span></span></div><div class="t m0 xd hf y55 ff8 fs9 fc0 sc0 ls64 ws83">Carry Logic<span class="_ _8"> </span><span class="ff6 fs2 ls54 ws5"> . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . <span class="ls65 ws84">. .<span class="_ _8"> </span> 43</span></span></div><div class="t m0 xe h10 y56 ff1 fsa fc0 sc0 ls66 ws85">Chapter<span class="_"> </span>3: Design Entry</div><div class="t m0 xd hf y57 ff8 fs9 fc0 sc0 ls5f ws7f">Design Checklist<span class="_ _10"> </span><span class="ff6 fs2 ls59 ws79">. . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> .<span class="_"> </span> 45</span></div><div class="t m0 xd hf y58 ff8 fs9 fc0 sc0 ls56 ws75">Using the CLB Resources<span class="_ _f"></span><span class="ff6 fs2 ls59 ws79">. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 46</span></div><div class="t m0 xd hf y59 ff8 fs9 fc0 sc0 ls67 ws5">Primitives<span class="_ _f"></span><span class="ff6 fs2 ls54">. . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . .<span class="ls68 ws86"> . . .<span class="_ _8"> </span> 46</span></span></div><div class="t m0 xe h10 y5a ff1 fsa fc0 sc0 ls5d ws7d">Chapter<span class="_"> </span>4: Applications</div><div class="t m0 xd hf y5b ff8 fs9 fc0 sc0 ls62 ws81">Distributed RAM Applications<span class="_ _10"> </span><span class="ff6 fs2 ls59 ws79">. . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 53</span></div><div class="t m0 xd hf y5c ff8 fs9 fc0 sc0 ls69 ws87">Shift Register Applications<span class="_ _e"></span><span class="ff6 fs2 ls59 ws79">. . . . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> .<span class="_ _8"> </span> 53</span></div><div class="t m0 xd hf y5d ff8 fs9 fc0 sc0 ls62 ws81">Carry Logic Applications<span class="_ _8"> </span><span class="ff6 fs2 ls59 ws79">. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . .<span class="_ _8"> </span> 55</span></div><div class="t m0 xe h10 y5e ff1 fsa fc0 sc0 ls5d ws7d">Chapter<span class="_"> </span>5: Timing</div><div class="t m0 xd hf y5f ff8 fs9 fc0 sc0 ls5f ws7f">CLB General Slice Timing Model and Parameters<span class="ff6 fs2 ls61 ws80">. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _8"> </span> 58</span></div><div class="t m0 xd hf y60 ff8 fs9 fc0 sc0 ls5e ws7e">CLB Slice Multiplexer Timing Model and Parameters<span class="_ _3"></span><span class="ff6 fs2 ls61 ws80">. . . . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . .<span class="_ _8"> </span> 60</span></div><div class="t m0 xd hf y61 ff8 fs9 fc0 sc0 ls56 ws75">CLB Slice Carry-Chain Timing Model and Parameters<span class="_ _3"></span><span class="ff6 fs2 ls61 ws80"> . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> .<span class="_ _8"> </span> 61</span></div><div class="t m0 x2 h11 y62 ff9 fsb fc0 sc0 ls6a ws88">Table of Contents</div><div class="c xf y63 w2 h12"><div class="t m2 x10 h13 y64 ffa fsc fc2 sc0 ls8 ws5"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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