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<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596586/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596586/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">7<span class="_"> </span>Series FPGAs</div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">Clocking Resources</div><div class="t m0 x1 h3 y3 ff2 fs1 fc0 sc0 ls1 ws1">User Guide</div><div class="t m0 x1 h4 y4 ff1 fs2 fc0 sc0 ls2 ws2"> UG472 (v1.14) Jul<span class="_ _0"></span>y 30, 2018</div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596586/bg2.jpg"><div class="t m0 x2 h5 y5 ff1 fs3 fc0 sc0 ls3 ws3">7<span class="_"> </span>Series FPGAs Clocking <span class="ws4">Resources User Guide<span class="_ _1"> </span><span class="ff3 fc1 ls4 ws5">www.xilinx.com<span class="_ _2"> </span><span class="fc0 ls5 ws6">UG472 (v1.14) July 30, 2018</span></span></span></div><div class="t m0 x2 h6 y6 ff3 fs4 fc0 sc0 ls6 ws7">The information disclosed to you hereunde<span class="_ _0"></span>r (the “Materials”) is prov<span class="ls7 ws8">ided<span class="_ _0"></span> solely for the selectio<span class="_ _0"></span>n and use of Xilinx products. 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You may not reproduce, modi<span class="ls14 ws23">fy, distribute<span class="_ _0"></span>, or publicly display th<span class="_ _0"></span>e Ma<span class="ls11 ws24">terials without prior w<span class="_ _0"></span>ritten consent. Cer<span class="ls13">tain products a<span class="_ _0"></span>re </span></span></span></div><div class="t m0 x2 h6 y10 ff3 fs4 fc0 sc0 ls19 ws25">subject to the terms and conditions of Xilinx’s limited warranty, pl<span class="ls6 ws26">ease refer to <span class="_ _0"></span>Xilinx’s Terms of Sale <span class="_ _0"></span>which can be viewed<span class="_ _0"></span> at<span class="ls1a ws5"> </span></span></div><div class="t m0 x2 h6 y11 ff3 fs4 fc1 sc0 ls14 ws5">www.xilinx.com/legal<span class="_ _0"></span>.htm#tos</div><div class="t m0 x3 h6 y12 ff3 fs4 fc0 sc0 ls16 ws27">; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. 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CUSTOMER SHALL, <span class="lsf ws32">PRIOR TO USING OR DIST<span class="ls1a ws33">RIBUTING ANY SYSTEMS THAT<span class="lsb ws2e"> INCORPORATE PRODUCTS, </span></span></span></div><div class="t m0 x2 h6 y1c ff3 fs4 fc0 sc0 lsf ws34">THOROUGHLY TEST SUCH SYSTEMS FOR <span class="_ _0"></span><span class="ls18 ws35">SAFETY PURPOSES. USE OF PRODUCTS IN<span class="lsf ws1a"> A SAFETY APPLICATION WITHOUT A </span></span></div><div class="t m0 x2 h6 y1d ff3 fs4 fc0 sc0 ls1c ws36">SAFETY DESIGN IS FULLY AT THE RISK OF<span class="ls17 ws37"> CUSTOMER, SUBJECT ONLY <span class="_ _3"></span>TO APPLIC<span class="lsb ws38">ABLE LAWS AND REGULATIONS GOVERNING </span></span></div><div class="t m0 x2 h6 y1e ff3 fs4 fc0 sc0 ls17 ws39">LIMITATIONS ON PR<span class="ls13 ws19">ODUCT LIABILITY. </span></div><div class="t m0 x2 h6 y1f ff3 fs4 fc0 sc0 ls7 ws3a">© Copyright 2011–2018 Xilinx, Inc. Xi<span class="_ _0"></span>linx, t<span class="ls15 ws3b">he Xilin<span class="_ _0"></span>x logo, Artix, ISE, Kintex, Sparta<span class="_ _0"></span><span class="ls1d ws3c">n, Virtex, Vivado, Zynq, and <span class="_ _0"></span>other design<span class="ls9 wsa">ated brands </span></span></span></div><div class="t m0 x2 h6 y20 ff3 fs4 fc0 sc0 ls9 ws20">included herein are trademarks of Xilinx in <span class="wsa">the United States and<span class="_ _0"></span> other countries. PC<span class="ls13 ws19">I, PCIe, and PCI Express are trademarks of<span class="ls1e ws3d"> PCI-SIG </span></span></span></div><div class="t m0 x2 h6 y21 ff3 fs4 fc0 sc0 ls9 wsa">and used under license. All other trademarks ar<span class="ls6 ws2a">e the property of their respective owners.</span></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596586/bg3.jpg"><div class="t m0 x2 h5 y5 ff3 fs3 fc0 sc0 ls1f ws3e">UG472 (v1.14) July 30, 2018<span class="_ _2"> </span><span class="fc1 ls4 ws5">www.xilinx.com<span class="_ _1"> </span></span><span class="ff1 ls20 ws4">7<span class="_"> </span>Series FPGAs Clocking Resources User Guide</span></div><div class="t m0 x2 h7 y22 ff1 fs5 fc0 sc0 ls21 ws3f">Revision History</div><div class="t m0 x2 h8 y23 ff4 fs2 fc0 sc0 ls22 ws40">The following table shows the revision history for this document.</div><div class="t m0 x2 h9 y24 ff3 fs6 fc0 sc0 ls23 ws5"> . </div><div class="t m0 x4 ha y25 ff1 fs7 fc0 sc0 ls24 ws5">Date<span class="_ _4"> </span>Version<span class="_ _5"> </span>Revision</div><div class="t m0 x5 hb y26 ff4 fs7 fc0 sc0 ls24 ws41">03/01/2011<span class="_ _6"> </span>1.0<span class="_ _7"> </span>Initial Xilinx release.</div><div class="t m0 x5 hb y27 ff4 fs7 fc0 sc0 ls25 ws42">03/28/2011<span class="_ _6"> </span>1.1<span class="_ _7"> </span>Updated disclaimer and copyright on <span class="_ _3"></span><span class="fc1 ls26 ws5">page<span class="_"> </span>2</span><span class="ls27 ws43">. Updated <span class="_ _3"></span><span class="fc1 ls28 ws44">Clocking Architecture Overview</span><span class="ls1a ws5"> </span></span></div><div class="t m0 x6 hb y28 ff4 fs7 fc0 sc0 ls29 ws5">and <span class="fc1 ls25">Figure<span class="_"> </span>2-2</span><span class="ls2a ws45">. Revised the discussion in <span class="fc1 ls2b ws46">Clock-C<span class="_ _0"></span>apable In<span class="_ _0"></span>puts<span class="fc0 ls2c ws47"> including adding </span></span></span></div><div class="t m0 x6 hb y29 ff4 fs7 fc0 sc0 ls2d ws48">Table<span class="_ _8"> </span>1-1 and <span class="fc1 ls25 ws5">Figure<span class="_"> </span>2-1</span><span class="ls2e ws49">. Revised some of the <span class="fc1 ls2f ws4a">Global Clock Buffers<span class="fc0 ls30"> descriptions. Revised </span></span></span></div><div class="t m0 x6 hb y2a ff4 fs7 fc0 sc0 ls2d ws4b">the description under <span class="fc1 ls28 ws5">Figure<span class="_"> </span>2-17</span><span class="ls31 ws4c">. Updated<span class="_ _3"></span> the <span class="fc1 ls32 ws4d">I/O Clock Buffer—BUFIO</span><span class="ls25 ws4e"> section. </span></span></div><div class="t m0 x6 hb y2b ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1 ls33">Figure<span class="_"> </span>2-20</span><span class="ls34 ws4f">. Updated the <span class="fc1 ls35 ws50">Regional Clock <span class="_ _3"></span>Buffer—BUFR</span><span class="ls28 ws51"> section. Updated the </span></span></div><div class="t m0 x6 hb y2c ff4 fs7 fc0 sc0 ls36 ws52">description in <span class="fc1 ls37 ws5">Table<span class="_"> </span>2-8</span><span class="ls38 ws53">. Revised <span class="fc1 ls30 ws5">Figure<span class="_"> </span>2-23</span><span class="ls39 ws54">. Added the BUFMRCE to the <span class="fc1 ls33 ws5">BUFMR </span></span></span></div><div class="t m0 x6 hb y2d ff4 fs7 fc1 sc0 ls3a ws5">Primitive<span class="fc0 ls24 ws41"> section including </span><span class="ls33">Figure<span class="_"> </span>2-25<span class="fc0 ls3b ws55">. Added BUFHCE to the<span class="_ _3"></span> </span><span class="ls26 ws56">Horizontal Clock </span></span></div><div class="t m0 x6 hb y2e ff4 fs7 fc1 sc0 ls39 ws57">Buffer—BUFH, BUFHCE<span class="fc0 ls2c ws58"> section. Moved <span class="_ _0"></span><span class="fc1 ls30 ws59">Clock Gating for Power Savings<span class="fc0 ls1a ws5">.</span></span></span></div><div class="t m0 x6 hb y2f ff4 fs7 fc0 sc0 ls3c ws5a">Updated the <span class="fc1 ls3d ws5b">MMCMs and PLLs<span class="_ _0"></span><span class="fc0 ls1a ws5c"> section. Revised the <span class="fc1 ls24 ws41">Frequency Synthesis Only Using </span></span></span></div><div class="t m0 x6 hb y30 ff4 fs7 fc1 sc0 ls24 ws5d">Integer Divide<span class="fc0 ls30 ws5e"> section including </span><span class="ls2a ws5">Figure<span class="_"> </span>3-4<span class="fc0 ls3e ws5f">. Revised the discussion around adjacent </span></span></div><div class="t m0 x6 hb y31 ff4 fs7 fc0 sc0 ls26 ws60">regions in <span class="fc1 ls3f ws61">CLKOUT[0:6] – O<span class="_ _3"></span>utput Clocks</span><span class="ls37 ws62">. <span class="_ _3"></span>Updated the e<span class="_ _3"></span>xamples after<span class="_ _3"></span> <span class="fc1 ls2d ws5">Equation<span class="_"> </span>3-11<span class="fc0 ls40">. </span></span></span></div><div class="t m0 x6 hb y32 ff4 fs7 fc0 sc0 ls2a ws45">Moved and revised <span class="fc1 ls3a ws63">VHDL and Verilog Templates and the Clocking Wizard</span><span class="ls1a ws5">.</span></div><div class="t m0 x6 hb y33 ff4 fs7 fc0 sc0 ls2a ws5">Added <span class="fc1 ls3a ws64">Appendix<span class="_"> </span>A, Multi-Region Clocking</span><span class="ls1a">.</span></div><div class="t m0 x5 hb y34 ff4 fs7 fc0 sc0 ls25 ws4e">05/31/2011<span class="_ _6"> </span>1.2<span class="_ _7"> </span>Added section on <span class="fc1 ls3a ws64">7<span class="_"> </span>Series FPGAs Clocking <span class="_ _3"></span>Differ<span class="ls41 ws65">ences from Prev<span class="_ _0"></span>ious FPGA </span></span></div><div class="t m0 x6 hb y35 ff4 fs7 fc1 sc0 ls39 ws5">Generations<span class="fc0 ls1a">.</span></div><div class="t m0 x6 hb y36 ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1 ls3e">Figure<span class="_"> </span>2-2</span><span class="ls35 ws50">. Clarified discussion in <span class="fc1 ws66">Clock-Capable Inputs</span><span class="ls42 ws67"> section <span class="_ _0"></span>includ<span class="_ _0"></span>ing </span></span></div><div class="t m0 x6 hc y37 ff4 fs7 fc0 sc0 ls2f ws68">removing Table<span class="_"> </span>1-1: <span class="ff5 ls2c ws47">Migration of devices in <span class="_ _3"></span>the same <span class="ls35 ws69">package with different top/bottom </span></span></div><div class="t m0 x6 hc y38 ff5 fs7 fc0 sc0 ls33 ws5">alignments<span class="ff4 ls43 ws6a">. Redrew <span class="fc1 ls2a ws5">Figure<span class="_"> </span>2-4<span class="fc0 ls44">, </span><span class="ls28">Figure<span class="_"> </span>2-16<span class="fc0 ls40">, <span class="_ _0"></span><span class="fc1 ls28">Figure<span class="_"> </span>2-18<span class="fc0 ls39 ws57">, and </span>Figure<span class="_"> </span>2-22<span class="fc0 ls1a">.</span></span></span></span></span></span></div><div class="t m0 x6 hb y39 ff4 fs7 fc0 sc0 ls2e ws6b">Updated description of <span class="fc1 ls35 ws5">CLKOUT[0:6]</span><span class="ls45 ws6c"> in </span><span class="fc1 ws5">Table<span class="_"> </span>3-5</span><span class="ls46 ws6d">.<span class="_ _0"></span> Updated <span class="fc1">CLKFBSTOPPED – </span></span></div><div class="t m0 x6 hb y3a ff4 fs7 fc1 sc0 ls35 ws69">Feedback Clock Status, page<span class="_"> </span>83<span class="fc0 ws66">. Clarified the MMCM/PLL relationship including </span></div><div class="t m0 x6 hb y3b ff4 fs7 fc0 sc0 ls2c ws5">updating <span class="fc1 ls30">Figure<span class="_"> </span>3-10</span><span class="ls47 ws6e">. Added more informat<span class="_ _3"></span>ion to the <span class="fc1 ls3a ws64">Phase Shift</span><span class="ls30 ws5e"> section, including </span></span></div><div class="t m0 x6 hb y3c ff4 fs7 fc1 sc0 ls48 ws5">Equation<span class="_"> </span>3-5<span class="_ _0"></span><span class="fc0 ls1a">.</span></div><div class="t m0 x6 hb y3d ff4 fs7 fc0 sc0 ls33 ws5">Revised <span class="fc1 ls2a">Figure<span class="_"> </span>A-6</span><span class="ls31 ws6f"> and </span></div><div class="t m0 x7 hb y3e ff4 fs7 fc1 sc0 ls2a ws5">Figure<span class="_"> </span>A-7<span class="fc0 ls31 ws4c">. Added </span><span class="ls2f ws70">Appendix<span class="_"> </span>B, Clocking Resources and </span></div><div class="t m0 x6 hb y3f ff4 fs7 fc1 sc0 ls49 ws71">Connectivity <span class="_ _3"></span>Variations per Clo<span class="_ _3"></span>ck Region<span class="fc0 ls1a ws5">.</span></div><div class="t m0 x5 hb y40 ff4 fs7 fc0 sc0 ls26 ws5">10/27/2011<span class="_ _6"> </span>1.3<span class="_ _7"> </span>Moved <span class="fc1 ls2f ws70">7<span class="_"> </span>Series FPGAs Clocking Differences from Previous FPGA Generations</span><span class="ls46 ws6d">. Added </span></div><div class="t m0 x6 hb y41 ff4 fs7 fc1 sc0 ls35 ws50">Clock Buffer Selection Considerations<span class="fc0 ls2f ws68">. Clarified descri<span class="_ _3"></span>ption in </span><span class="ls36 ws52">Clock-Capable Inputs<span class="fc0 ls40 ws5">. </span></span></div><div class="t m0 x6 hb y42 ff4 fs7 fc0 sc0 ls4a ws72">Added another note after <span class="fc1 ls3a ws63">Figure<span class="_"> </span>2-22, page<span class="_"> </span>53</span><span class="ls4b ws73">. Added the <span class="fc1 ls33 ws74">Stacked Silicon Interc<span class="_ _3"></span>onnect </span></span></div><div class="t m0 x6 hb y43 ff4 fs7 fc1 sc0 ls33 ws5">Clocking<span class="fc0 ls1a ws75"> section.</span></div><div class="t m0 x6 hb y44 ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1 ls1a ws75">Figure<span class="_"> </span>3-6, page<span class="_"> </span>73</span><span class="ls2c ws58">. Clarified descriptions in <span class="fc1 ls24 ws5d">Frequency Synthesis Using </span></span></div><div class="t m0 x6 hb y45 ff4 fs7 fc1 sc0 ls4c ws76">Fractional Divide<span class="_ _3"></span> in the MMCM<span class="_ _3"></span>, page<span class="_"> </span>73<span class="fc0 ls44 ws5">, <span class="_ _3"></span></span><span class="ls25 ws4e">Interpolated Fine Phase Shift in Fixed or </span></div><div class="t m0 x6 hb y46 ff4 fs7 fc1 sc0 ls3f ws77">Dynamic Mode in the MMCM, page<span class="_"> </span>75<span class="fc0 ls40 ws5">, </span><span class="ls29 ws78">Determine the Input Frequency, page<span class="_"> </span>76<span class="_ _0"></span><span class="fc0 ls40 ws5">, </span></span></div><div class="t m0 x6 hb y47 ff4 fs7 fc1 sc0 ls4d ws79">CLKOUT[0:6] – Output<span class="_ _3"></span> Clocks, page<span class="_"> </span>8<span class="_ _3"></span>2<span class="fc0 ls27 ws7a">, and </span><span class="ls1a ws75">Reference Clock Switching, page<span class="_"> </span>91<span class="_ _3"></span><span class="fc0 ls44 ws5">. </span></span></div><div class="t m0 x6 hb y48 ff4 fs7 fc0 sc0 ls2f ws7b">Revised description of <span class="fc1 ls4a ws7c">STARTUP_WAIT, page<span class="_ _8"> </span>85</span><span class="ls31 ws7d">. Updated <span class="fc1 ls4e ws5">RST</span><span class="ls25 ws7e"> description in </span></span><span class="fc1 ws5">Table<span class="_"> </span>3-5, </span></div><div class="t m0 x6 hb y49 ff4 fs7 fc1 sc0 ls35 ws5">page<span class="_"> </span>78<span class="fc0 ls4f ws7f">. Updated </span><span class="ls3a">CLKOUT[0]_DIVIDE_F(2)</span><span class="fc0 ws69"> allowed values in </span><span class="ls45 ws80">Table<span class="_"> </span>3-7, page<span class="_"> </span>83</span><span class="fc0 ls44">. </span></div><div class="t m0 x6 hb y4a ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1 ls2f ws70">Clock Network Deskew, page<span class="_"> </span>72</span><span class="ls26 ws56"> adding <span class="fc1 ws64">Figure<span class="_"> </span>3-12, page<span class="_"> </span>92</span></span><span class="ls1a">.</span></div><div class="t m0 x6 hb y4b ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1">Table<span class="_"> </span>B-1</span><span class="ls33 ws81"> and added </span><span class="fc1 ls4d">Table<span class="_"> </span>B-2</span><span class="ls1a">.</span></div><div class="t m0 x5 hb y4c ff4 fs7 fc0 sc0 ls30 ws82">02/16/2012<span class="_ _6"> </span>1.4<span class="_ _7"> </span>Replaced “clocking backbone” with “clock backbone” and “clocking region” with “clock </div><div class="t m0 x6 hb y4d ff4 fs7 fc0 sc0 ls3f ws61">region” throughout.</div><div class="t m0 x6 hb y4e ff4 fs7 fc0 sc0 ls2a ws5">Added <span class="fc1 ls2f ws83">Chapter<span class="_"> </span>1, Clocking Overview</span><span class="ls3a ws84">, containing <span class="fc1 ls24 ws85">7<span class="_"> </span>Series FPGAs Clocking Differences </span></span></div><div class="t m0 x6 hb y4f ff4 fs7 fc1 sc0 ls2d ws86">from Previous FP<span class="_ _3"></span>GA Generations<span class="fc0 ls50 ws87"> fr<span class="_ _3"></span>om </span><span class="ls51 ws5">Chapt<span class="_ _0"></span>er<span class="_"> </span>2<span class="fc0 ls52 ws88"> and <span class="_ _0"></span><span class="fc1 ls53 ws89">Summary of Clock Connectivity<span class="fc0 ls1a ws5"> </span></span></span></span></div><div class="t m0 x6 hb y50 ff4 fs7 fc0 sc0 ls2f ws70">from Appendix<span class="_"> </span>B. Updated <span class="fc1 ls27 ws5">Table<span class="_"> </span>1-1</span><span class="ls30 ws59">. Removed XC7A8, XC7A15, XC7A3<span class="_ _3"></span>0T, and </span></div><div class="t m0 x6 hb y51 ff4 fs7 fc0 sc0 ls2f ws68">XC7A50T from <span class="fc1 ls2e ws5">Table<span class="_"> </span>1-2<span class="fc0 ls1a">.</span></span></div><div class="t m0 x6 hb y52 ff4 fs7 fc0 sc0 ls2a ws5">Added <span class="fc1 ls1a ws5c">Clock-Capable Inputs</span><span class="ls4e ws8a">. Updated <span class="fc1 ls46 ws8b">Global Clocking Resources</span></span><span class="ws45">, including </span><span class="fc1 ls33">BUFMR </span></div><div class="t m0 x6 hb y53 ff4 fs7 fc1 sc0 ls3a ws5">Primitive<span class="fc0 ls4e ws8a">. Updated </span><span class="ls30 ws59">Horizontal Clock Buffer—BUFH, BUFHCE<span class="fc0 ls25 ws66">. Updated paragraph </span></span></div><div class="t m0 x6 hb y54 ff4 fs7 fc0 sc0 ls2f ws5">before <span class="fc1 ls28">Figure<span class="_"> </span>2-27</span><span class="ls1a">.</span></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596586/bg4.jpg"><div class="t m0 x2 h5 y5 ff1 fs3 fc0 sc0 ls3 ws3">7<span class="_"> </span>Series FPGAs Clocking <span class="ws4">Resources User Guide<span class="_ _1"> </span><span class="ff3 fc1 ls4 ws5">www.xilinx.com<span class="_ _2"> </span><span class="fc0 ls5 ws6">UG472 (v1.14) July 30, 2018</span></span></span></div><div class="t m0 x5 hb y55 ff4 fs7 fc0 sc0 ls24 ws5">02/16/2012<span class="_ _6"> </span>1.4</div><div class="t m0 x8 hc y56 ff5 fs7 fc0 sc0 ls45 ws5">(Cont’d)</div><div class="t m0 x6 hb y55 ff4 fs7 fc0 sc0 ls36 ws52">In introductory paragraph of <span class="fc1 ls35 ws50">High-Performance Clocks</span><span class="ls47 ws6e">, removed de<span class="_ _3"></span>scription of HPCs </span></div><div class="t m0 x6 hc y56 ff4 fs7 fc0 sc0 ls2a ws8c">connecting to OSERDES and buffers.<span class="_ _0"></span><span class="ls30 ws8d"> Replaced cross reference to <span class="fc1 ls3a ws5">UG429<span class="fc0 ls44">, <span class="ff5 ls54 ws8e">7<span class="_"> </span>Series<span class="_ _3"></span> FPGAs </span></span></span></span></div><div class="t m0 x6 hc y57 ff5 fs7 fc0 sc0 ls25 ws4e">Migration Methodology Guide<span class="ff4 ls55 ws8f">, with <span class="fc1 ls27 ws5">UG872</span></span></div><div class="t m0 x9 hc y58 ff4 fs7 fc0 sc0 ls44 ws5">, <span class="ff5 ls24 ws5d">Large FPGA Methodology Guide</span><span class="ls52 ws90">. Updated </span></div><div class="t m0 x6 hb y59 ff4 fs7 fc1 sc0 ls36 ws91">Stacked Silicon Interconnect Clocking<span class="_ _3"></span><span class="fc0 ws52">. Replaced SRL with SLR in </span><span class="ls33 ws5">Figure<span class="_"> </span>2-29<span class="fc0 ls31 ws4c">. Added<span class="_ _3"></span> </span></span></div><div class="t m0 x6 hb y5a ff4 fs7 fc1 sc0 ls28 ws5">Figure<span class="_"> </span>2-31<span class="fc0 ls1a">.</span></div><div class="t m0 x6 hb y5b ff4 fs7 fc0 sc0 ls56 ws92">Removed hold bloc<span class="_ _3"></span>k from <span class="fc1 ls2a ws5">Figure<span class="_"> </span>3-2</span><span class="ls49 ws93">. Update<span class="_ _3"></span>d clock frequencies in <span class="fc1 ls24 ws94">Frequency Syn<span class="_ _3"></span>thesis </span></span></div><div class="t m0 x6 hb y5c ff4 fs7 fc1 sc0 ls4a ws95">Only Using Integer Divide<span class="fc0 ls24 ws5d">. Replaced 64 with 63 in </span><span class="ls1a ws5">Equation<span class="_"> </span>3-4<span class="fc0 ls31 ws4c">. Updated<span class="_ _3"></span> </span><span class="ls3a">Interpolated </span></span></div><div class="t m0 x6 hb y5d ff4 fs7 fc1 sc0 ls25 ws66">Fine Phase Shift in Fixed or Dynamic Mode in the MMCM<span class="fc0 ls2f ws70">. Updated pin description of </span></div><div class="t m0 x6 hb y5e ff4 fs7 fc0 sc0 ls4a ws95">LOCKED in <span class="fc1 ls2e ws5">Table<span class="_"> </span>3-5</span><span class="ls57 ws96">. Updated <span class="fc1 ls58 ws5">LOCK<span class="_ _0"></span>ED<span class="fc0 ls59 ws97">. In </span><span class="ls27">Table<span class="_"> </span>3-7<span class="fc0 ls52 ws90">, updated type and allowed </span></span></span></span></div><div class="t m0 x6 hb y5f ff4 fs7 fc0 sc0 ls25 ws4e">values of CLKOUT[0]_DIVIDE_F and CL<span class="_ _3"></span><span class="ls29 ws98">KFBOUT_MULT_F, and description of </span></div><div class="t m0 x6 hb y60 ff4 fs7 fc0 sc0 ls5a ws76">STARTU<span class="_ _0"></span>P_WAIT<span class="_ _0"></span> and CO<span class="_ _0"></span>MPENSATI<span class="_ _0"></span>ON. I<span class="_ _0"></span>n <span class="fc1 ls26 ws5">Table<span class="_"> </span>3-8</span><span class="ls5b ws99">, added STARTUP_WAIT and<span class="_ _0"></span> </span></div><div class="t m0 x6 hb y61 ff4 fs7 fc0 sc0 ls28 ws51">updated description of COMPENSATI<span class="ls29 ws98">ON. Replaced GTX with GT in </span><span class="fc1 ws5">Figure<span class="_"> </span>3-10<span class="fc0 ls44">. </span></span></div><div class="t m0 x6 hb y62 ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1 ls33 ws81">Dynamic Reconfiguration Port</span><span class="ls1a">.</span></div><div class="t m0 x6 hb y63 ff4 fs7 fc0 sc0 ls2a ws5">Added <span class="fc1 ls35 ws9a">Appendix<span class="_"> </span>B, Clocking Resources and Co<span class="ls2f ws83">nnectivity Variations per Clock Region</span></span><span class="ls1a">.</span></div><div class="t m0 x5 hb y64 ff4 fs7 fc0 sc0 ls26 ws60">07/13/2012<span class="_ _6"> </span>1.5<span class="_ _7"> </span>Updated paragraph after <span class="fc1 ls3e ws5">Figure<span class="_"> </span>1-4</span><span class="ls24 ws41">. Added bullet about spread</span><span class="ws56"> spectrum support to </span></div><div class="t m0 x6 hb y65 ff4 fs7 fc1 sc0 ls45 ws6c">Key Differences from Virtex-6 <span class="_ _0"></span>FPGAs<span class="fc0 ls52 ws90">. Updated BUFG and BUFH pins, and removed </span></div><div class="t m0 x6 hb y66 ff4 fs7 fc0 sc0 ls25 ws4e">IBUFDS_GTE2.O/IBUFDS_GTE2.ODIV2 pin from <span class="_ _3"></span><span class="fc1 ls27 ws5">Table<span class="_"> </span>1-1</span><span class="ls5c ws9b">. U<span class="_ _3"></span>pdated <span class="fc1 ls26 ws5">Table<span class="_"> </span>1-2<span class="fc0 ls1a">.</span></span></span></div><div class="t m0 x6 hb y67 ff4 fs7 fc0 sc0 ls5b ws9c">Updated note 5 in <span class="fc1 ls2e ws5">Table<span class="_"> </span>2-1</span><span class="ls31 ws4c">. Added <span class="fc1 ls35 ws5">Figure<span class="_"> </span>2-29<span class="fc0 ls1a">.</span></span></span></div><div class="t m0 x6 hb y68 ff4 fs7 fc0 sc0 ls2e ws9d">Updated last sentence of <span class="_ _0"></span><span class="fc1 ls49 ws5">Introduction<span class="fc0 ls27 ws9e">. Updat<span class="_ _3"></span>ed </span><span class="ls2f ws70">DO[15:0] – Dynamic Reconfiguration </span></span></div><div class="t m0 x6 hb y69 ff4 fs7 fc1 sc0 ls47 ws6e">Output Bus<span class="fc0 ls25 ws66">. Added SS_EN, SS_MODE, <span class="ls2f ws68">and SS_MOD_PERIOD <span class="_ _3"></span>to </span></span><span class="ls2e ws5">Table<span class="_"> </span>3-7<span class="fc0 ls31 ws4c">. Added </span></span></div><div class="t m0 x6 hb y6a ff4 fs7 fc1 sc0 ls3a ws63">Spread-Spectrum Clock Generation<span class="fc0 ls1a ws5">.</span></div><div class="t m0 x5 hb y6b ff4 fs7 fc0 sc0 ls3a ws64">10/02/2012<span class="_ _6"> </span>1.6<span class="_ _7"> </span>Added note to <span class="fc1 ls2e ws5">Table<span class="_"> </span>1-1</span><span class="ls4d ws9f">. Removed XC7A350T and XC7V1500T from <span class="fc1 ls2e ws5">Table<span class="_"> </span>1-2<span class="fc0 ls1a">.</span></span></span></div><div class="t m0 x6 hb y6c ff4 fs7 fc0 sc0 ls24 wsa0">Updated first paragraph of <span class="fc1 ls30 wsa1">Single Clock Driving Multiple CMTs</span><span class="ls1a wsa2">. Added notes 5 and 8 to </span></div><div class="t m0 x6 hb y6d ff4 fs7 fc1 sc0 ls30 ws5">Table<span class="_"> </span>2-1<span class="fc0 ls2d ws86">. Updated par<span class="_ _3"></span>agraph after </span><span class="ls45">Table<span class="_"> </span>2-10<span class="fc0 ls1a">.</span></span></div><div class="t m0 x6 hb y6e ff4 fs7 fc0 sc0 ls2a ws5">Added <span class="fc1 ls2e">Table<span class="_"> </span>3-9</span><span class="ls36 ws52"> and timing constraint calculations for 25<span class="_"> </span>MHz and 80<span class="_"> </span>MHz input </span></div><div class="t m0 x6 hb y6f ff4 fs7 fc0 sc0 ls4c wsa3">clocks. In <span class="fc1 ls30 ws5">Table<span class="_"> </span>3-10</span><span class="ls2a ws45">, changed Bandwidth value from N/A to Low, and removed </span></div><div class="t m0 x6 hb y70 ff4 fs7 fc0 sc0 ls2c ws47">duplicate paragraph after table.</div><div class="t m0 x6 hb y71 ff4 fs7 fc0 sc0 ls2f ws68">Removed XC7A350T from title of <span class="_ _3"></span><span class="fc1 ls4a ws5">Figure<span class="_"> </span>B-4<span class="fc0 ls1a">.</span></span></div><div class="t m0 x5 hb y72 ff4 fs7 fc0 sc0 ls26 ws5">04/03/2013<span class="_ _6"> </span>1.7<span class="_ _7"> </span>Updated <span class="fc1 ls3e">Figure<span class="_"> </span>1-3</span><span class="ls40">, <span class="fc1 ls2f">Figure<span class="_"> </span>B-2</span><span class="ls39 ws57">, and </span><span class="fc1 ls2f">Figure<span class="_"> </span>B-3</span><span class="ls39 ws57">. Added BUFMR to </span><span class="fc1 ls5d">Table<span class="_ _8"> </span>1<span class="_ _3"></span>-1</span></span></div><div class="t m0 xa hb y73 ff4 fs7 fc0 sc0 ls27 ws9e">. Updated </div><div class="t m0 x6 hb y74 ff4 fs7 fc0 sc0 ls24 ws41">second paragraph in <span class="fc1 ls30 ws5e">Dynamic Phase Shift Interface in the MMCM<span class="_ _3"></span></span><span class="ls5e wsa4">. Added note to </span></div><div class="t m0 x6 hb y75 ff4 fs7 fc1 sc0 ls30 ws5">Table<span class="_"> </span>2-7<span class="fc0 ls1a">.</span></div><div class="t m0 x5 hb y76 ff4 fs7 fc0 sc0 ls26 ws5">08/07/2013<span class="_ _6"> </span>1.8<span class="_ _7"> </span>Updated <span class="_ _9"></span><span class="fc1 ls2e">Table<span class="_"> </span>1-2<span class="fc0 wsa5"> and </span>Table<span class="_"> </span>3-7<span class="fc0 ls3b wsa6">. Updated the figure t<span class="_ _3"></span>itles for <span class="_ _3"></span></span><span class="ls4a">Figure<span class="_"> </span>B-2<span class="fc0 ls29 wsa7"> and </span><span class="ls2f">Figure<span class="_"> </span>B-3<span class="fc0 ls40">. </span></span></span></span></div><div class="t m0 x6 hb y77 ff4 fs7 fc0 sc0 ls2e ws5">Updated <span class="fc1 ls28 ws51">Clock Buffer Placement</span><span class="ls1a">.</span></div><div class="t m0 x5 hb y78 ff4 fs7 fc0 sc0 ls26 ws5">04/08/2014<span class="_ _6"> </span>1.9<span class="_ _7"> </span>Updated <span class="fc1 ls5f wsa8">Clock-Capable Inputs</span><span class="ws60"> and <span class="fc1 ls25 ws66">Dynamic Phase Shift Interface in the MMCM</span></span><span class="ls44">. </span></div><div class="t m0 x6 hb y79 ff4 fs7 fc0 sc0 ls29 ws98">Updated allowed values and the de<span class="ls4a ws72">fault value for CLKFBOUT_MULT in <span class="fc1 ls27 ws5">Table<span class="_"> </span>3-8<span class="fc0 ls1a">.</span></span></span></div><div class="t m0 x5 hb y7a ff4 fs7 fc0 sc0 ls2f ws83">05/24/2014<span class="_ _a"> </span>1.10<span class="_ _b"> </span>Changed the value of minimum <span class="ls26 wsa9">clock regions from six to four in <span class="fc1 ls30 wsaa">Clocking Architecture </span></span></div><div class="t m0 x6 hb y7b ff4 fs7 fc1 sc0 ls36 ws5">Overview<span class="fc0 ls4a ws72">. Added information to MGTREFCLK0 in </span><span class="ls37">Ta<span class="_ _3"></span>ble<span class="_"> </span>1-1<span class="fc0 ls38 ws53">. Added section on </span><span class="ls60">GTZ </span></span></div><div class="t m0 x6 hb y7c ff4 fs7 fc1 sc0 ls5e wsa4">Loopback Clock Buffer — BUFG_LB (HT <span class="_ _0"></span>devices only)<span class="fc0 ls52 ws90"> to Chapter 2. Changed </span></div><div class="t m0 x6 hb y7d ff4 fs7 fc0 sc0 ls45 wsab">description of REF_JITTE<span class="_ _0"></span>R1 and REF_JITTER2 in <span class="fc1 ls26 ws5">Table<span class="_"> </span>3-7</span><span class="ls29 wsac"> and <span class="fc1 ls5d ws5">Table<span class="_"> </span>3-8<span class="_ _3"></span></span><span class="ls39 wsad">. Updated first </span></span></div><div class="t m0 x6 hb y7e ff4 fs7 fc0 sc0 ls25 ws66">paragraph in <span class="fc1 ls2d ws4b">Use Cases</span><span class="ls1a ws5">.</span></div><div class="t m0 x5 hb y7f ff4 fs7 fc0 sc0 ls36 ws52">11/19/2014<span class="_ _a"> </span>1.11<span class="_ _b"> </span>Removed general interco<span class="ls30 ws5e">nnect from this bulleted list on <span class="_ _3"></span><span class="fc1 ls35 ws5">page<span class="_"> </span>49</span><span class="ls31 ws4c">. Update<span class="_ _3"></span>d the figure </span></span></div><div class="t m0 x6 hb y80 ff4 fs7 fc0 sc0 ls50 ws87">titles for <span class="fc1 ls3f ws5">Figure<span class="_ _8"> </span>B-2<span class="_ _3"></span></span><span class="ls52 ws88"> and <span class="fc1 ls2e ws5">Figure<span class="_"> </span>B-3<span class="fc0 ls1a">.</span></span></span></div><div class="t m0 x5 hb y81 ff4 fs7 fc0 sc0 ls3a ws5">03/04/2015<span class="_ _b"> </span>1.11.1<span class="_ _c"> </span>Updated <span class="fc1 ls35 ws50">Frequency Synthesis Using Fractional Divide in the <span class="_ _3"></span>MMCM, page<span class="_"> </span>73</span><span class="ls55 wsae"> by </span></div><div class="t m0 x6 hb y82 ff4 fs7 fc0 sc0 ls25 ws5">changing </div><div class="t m0 xb h8 y83 ff4 fs2 fc0 sc0 ls61 wsaf">0.125 degrees to 0.125<span class="_ _3"></span><span class="fs7 ls1a ws5">.</span></div><div class="t m0 x5 hc y84 ff4 fs7 fc0 sc0 ls26 wsb0">06/12/2015<span class="_ _b"> </span>1.11.2<span class="_ _c"> </span>Fixed broken link in three references to <span class="ff5 ls4a wsb1">7<span class="_ _8"> </span>Series FPGA Data Sheets</span><span class="ls56 ws92"> on <span class="fc1 ls35 ws5">page<span class="_"> </span>73</span><span class="ls29 wsa5"> and <span class="fc1 ls35 ws5">page<span class="_"> </span>74<span class="fc0 ls1a">.</span></span></span></span></div><div class="t m0 x5 hb y85 ff4 fs7 fc0 sc0 ls4a ws72">09/27/2016<span class="_ _a"> </span>1.12<span class="_ _b"> </span>Added the Spartan-7 FPGAs and the <span class="ls2f ws70">Artix-7 (XC7A12T and XC7A25T) devices where </span></div><div class="t m0 x6 hb y86 ff4 fs7 fc0 sc0 ls25 ws4e">applicable including updating <span class="fc1 ls1a ws5">Appendix<span class="_"> </span>B<span class="fc0 ls44">.<span class="_ _3"></span> Updated <span class="_ _3"></span>the </span><span class="ls5f wsa8">BU<span class="_ _3"></span>FR Alignment</span></span><span class="ls2f ws70"> section. </span></div><div class="t m0 x6 hb y87 ff4 fs7 fc0 sc0 ls3c ws5a">Updated the <span class="fc1 ls26 ws60">Automotive Applications Disclaimer</span><span class="ls1a ws5">.</span></div><div class="t m0 x4 ha y88 ff1 fs7 fc0 sc0 ls24 ws5">Date<span class="_ _4"> </span>Version<span class="_ _5"> </span>Revision</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89596586/bg5.jpg"><div class="t m0 x2 h5 y5 ff3 fs3 fc0 sc0 ls1f ws3e">UG472 (v1.14) July 30, 2018<span class="_ _2"> </span><span class="fc1 ls4 ws5">www.xilinx.com<span class="_ _1"> </span></span><span class="ff1 ls20 ws4">7<span class="_"> </span>Series FPGAs Clocking Resources User Guide</span></div><div class="t m0 x5 hb y55 ff4 fs7 fc0 sc0 ls2c ws47">03/01/2017<span class="_ _a"> </span>1.13<span class="_ _b"> </span>Updated the <span class="fc1 ls4a">BUFR Alignment</span><span class="ls3a ws63"> section.</span></div><div class="t m0 x5 hb y89 ff4 fs7 fc0 sc0 ls35 ws50">07/30/2018<span class="_ _a"> </span>1.14<span class="_ _b"> </span>Updated the example in <span class="fc1 ls28 ws51">Determine the Input Frequency</span><span class="ls1a ws75"> section.</span></div><div class="t m0 x4 ha y8a ff1 fs7 fc0 sc0 ls24 ws5">Date<span class="_ _4"> </span>Version<span class="_ _5"> </span>Revision</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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