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<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595080/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595080/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">DS180 (v1.13) November 30, 2012<span class="_ _0"> </span><span class="fc1 ls1 ws1">www<span class="_ _1"></span>.xilinx.com</span></div><div class="t m0 x1 h2 y2 ff2 fs0 fc0 sc0 ls2 ws2">Adv<span class="_ _1"></span>a<span class="_ _2"></span>nce Product Specificatio<span class="_ _2"></span>n<span class="_ _3"> </span><span class="ff1 ls3 ws1">1</span></div><div class="t m0 x1 h3 y3 ff1 fs1 fc0 sc0 ls4 ws3">© Copy<span class="_ _4"></span>right 2010–2012 Xilinx, Inc.,<span class="_ _4"></span> Xilinx, the Xilinx logo<span class="_ _1"></span>, Ar<span class="_ _2"></span>tix, ISE, Kinte<span class="_ _1"></span>x, Spar<span class="_ _2"></span>tan, Virtex, Zynq, and other designated br<span class="_ _1"></span><span class="ls5 ws4">ands included herein are trademarks of Xilinx in the </span></div><div class="t m0 x1 h3 y4 ff1 fs1 fc0 sc0 ls6 ws4">United States and other countries<span class="_ _4"></span>. PCI Express is a trademark of PCI-SIG and used under license<span class="_ _1"></span>. <span class="_ _2"></span>All other tr<span class="_ _4"></span>ademarks are the p<span class="ls7 ws5">roperty of <span class="_ _2"></span>their respectiv<span class="_ _1"></span>e owners.</span></div><div class="t m0 x1 h4 y5 ff2 fs2 fc0 sc0 ls8 ws6">General Description</div><div class="t m0 x1 h5 y6 ff1 fs3 fc0 sc0 ls9 ws7">Xilinx® 7<span class="_"> </span>series FPGAs compr<span class="_ _2"></span>ise three new FPGA f<span class="_ _1"></span>amilies that addr<span class="lsa ws8">ess the comple<span class="_ _2"></span>te range of system requirements, r<span class="_ _4"></span>anging from low<span class="lsb ws1"> cost, small f<span class="_ _1"></span>or<span class="_ _2"></span>m </span></span></div><div class="t m0 x1 h5 y7 ff1 fs3 fc0 sc0 lsc ws9">factor<span class="_ _1"></span>, cost-sensitiv<span class="_ _1"></span>e, high-volume applic<span class="ws7">ations to ultra high-end c<span class="lsd wsa">onnectivity bandwidth, logic c<span class="lse wsb">apacity<span class="_ _5"></span>, and signal processin<span class="lsf wsc">g capability for the most </span></span></span></span></div><div class="t m0 x1 h5 y8 ff1 fs3 fc0 sc0 lsa wsc">demanding high-performance applications. The 7<span class="_"> </span>series devices are <span class="ls10 wsd">the progr<span class="_ _1"></span>ammable silicon foundation f<span class="_ _1"></span>or T<span class="_ _5"></span>argeted Design Platfo<span class="ls11 wse">rms that enable </span></span></div><div class="t m0 x1 h5 y9 ff1 fs3 fc0 sc0 ls12 wsf">designers to focus on innov<span class="_ _1"></span>a<span class="_ _2"></span>tion from the outset of <span class="ls13 ws10">their development cycle<span class="_ _4"></span>. The 7<span class="_"> </span>series FPGAs include:</span></div><div class="t m0 x1 h5 ya ff1 fs3 fc0 sc0 ls11 wse">•<span class="_ _6"> </span>Ar<span class="_ _2"></span>tix™-7 F<span class="_ _1"></span>amily: Optimized for lo<span class="_ _1"></span>west cost and power with small </div><div class="t m0 x2 h5 yb ff1 fs3 fc0 sc0 lsf wsc">form-f<span class="_ _4"></span>actor packaging f<span class="_ _1"></span>or the highest volume applications.</div><div class="t m0 x1 h5 yc ff1 fs3 fc0 sc0 ls14 ws11">•<span class="_ _6"> </span>Kintex™-7 F<span class="_ _1"></span>amily: Optimized for <span class="ls10 wsd">best price-perf<span class="_ _4"></span>ormance<span class="_ _2"></span> with a 2X </span></div><div class="t m0 x2 h5 yd ff1 fs3 fc0 sc0 ls9 ws12">improv<span class="_ _1"></span>emen<span class="_ _2"></span>t compared to prev<span class="_ _4"></span>ious<span class="lsa ws13"> generation, enabling a ne<span class="_ _1"></span>w class </span></div><div class="t m0 x2 h5 ye ff1 fs3 fc0 sc0 lsd wsa">of FPGAs.</div><div class="t m0 x3 h5 yf ff1 fs3 fc0 sc0 ls10 wsd">•<span class="_ _6"> </span>Vir<span class="_ _2"></span>tex®-7 F<span class="_ _5"></span>amily: Optimized <span class="ls11 wse">for highest system performance and </span></div><div class="t m0 x4 h5 y10 ff1 fs3 fc0 sc0 lsf wsc">capacity with a 2X improv<span class="_ _1"></span>e<span class="_ _2"></span>ment <span class="ls3 ws14">in system performance. Highest </span></div><div class="t m0 x4 h5 y11 ff1 fs3 fc0 sc0 ls11 wse">capability devices enab<span class="_ _1"></span>l<span class="_ _2"></span>ed by st<span class="lsd wsa">ac<span class="_ _1"></span>ked silicon interconnect (SSI) </span></div><div class="t m0 x4 h5 y12 ff1 fs3 fc0 sc0 lsd ws1">technology<span class="_ _5"></span>.</div><div class="t m0 x1 h5 y13 ff1 fs3 fc0 sc0 ls13 ws10">Built on a state-of-the-ar<span class="_ _2"></span>t, high-performance<span class="lsd wsa">, low-po<span class="_ _4"></span>wer (HPL), 28<span class="_"> </span>nm, high-k metal gat<span class="lse wsb">e (HKMG) process te<span class="ls13 ws15">chnology<span class="_ _5"></span>, 7<span class="_"> </span>series FPGA<span class="ls15 ws16">s enable an </span></span></span></span></div><div class="t m0 x1 h5 y14 ff1 fs3 fc0 sc0 lsc ws17">unparalleled increase in system perf<span class="_ _4"></span>ormance with 2.9<span class="_ _7"> </span>Tb/s of I/O bandwidth, 2 million logic cell capacity<span class="_ _5"></span>, and 5.3<span class="_ _7"> </span>TMA<span class="_ _1"></span>C/s D<span class="_ _2"></span>SP<span class="_ _8"></span>, wh<span class="ls13 ws18">ile consuming 50% less </span></div><div class="t m0 x1 h5 y15 ff1 fs3 fc0 sc0 lsf wsc">power than pre<span class="_ _1"></span>vious generation devices to off<span class="_ _1"></span>er a fully programmable alternative to ASSPs and ASICs. Al<span class="_ _4"></span>l 7<span class="_"> </span>series devices share <span class="ls9 ws7">a scalab<span class="_ _4"></span>le, optimized </span></div><div class="t m0 x1 h5 y16 ff1 fs3 fc0 sc0 ls11 ws7">fourth-generation Advanced Silicon Modular Bl<span class="lsa ws8">ock (ASMBL™) column-based architecture that reduces system de<span class="_ _1"></span>velopment and deploym<span class="ls3 ws19">ent time <span class="_ _4"></span>with </span></span></div><div class="t m0 x1 h5 y17 ff1 fs3 fc0 sc0 lsc ws9">simplified design por<span class="_ _2"></span>tability<span class="_ _5"></span>. </div><div class="t m0 x1 h4 y18 ff2 fs2 fc0 sc0 ls16 ws1a">Summary of 7<span class="_"> </span>Series F<span class="_ _2"></span>PGA Features</div><div class="t m0 x1 h5 y19 ff1 fs3 fc0 sc0 ls11 wse">•<span class="_ _6"> </span>Advanced high-perf<span class="_ _1"></span>or<span class="_ _2"></span>mance FPGA logic based on real 6-input look-</div><div class="t m0 x2 h5 y1a ff1 fs3 fc0 sc0 lsa ws8">up table (LUT) technology configurab<span class="_ _1"></span>le as distr<span class="_ _2"></span>ibuted memory<span class="_ _5"></span>.</div><div class="t m0 x1 h5 y1b ff1 fs3 fc0 sc0 lsa ws8">•<span class="_ _6"> </span>36<span class="_"> </span>Kb dual-por<span class="_ _2"></span>t bloc<span class="_ _4"></span>k RAM with built-<span class="ls11 wse">in FIFO logic f<span class="_ _1"></span>or on-chip data </span></div><div class="t m0 x2 h5 y1c ff1 fs3 fc0 sc0 ls17 ws1">buf<span class="_ _2"></span>fer<span class="_ _2"></span>i<span class="_ _2"></span>n<span class="_ _2"></span>g.</div><div class="t m0 x1 h5 y1d ff1 fs3 fc0 sc0 ls11 wse">•<span class="_ _6"> </span>High-performance SelectIO™ te<span class="lsf wsc">chnology with suppor<span class="_ _2"></span>t for DDR3 </span></div><div class="t m0 x2 h5 y1e ff1 fs3 fc0 sc0 ls18 ws1b">interfaces up to 1,866 Mb/s.</div><div class="t m0 x1 h5 y1f ff1 fs3 fc0 sc0 lsa ws8">•<span class="_ _6"> </span>High-speed serial connectivity with built-in<span class="fc2 ls3 ws1"> </span><span class="lsf wsc">multi-gigabit transceiv<span class="_ _1"></span>ers </span></div><div class="t m0 x2 h5 y20 ff1 fs3 fc0 sc0 ls10 wsd">from 600<span class="_"> </span>Mb/s to maximum rates of 6.6<span class="_"> </span>Gb/s up to 28.05<span class="_"> </span>Gb/s, </div><div class="t m0 x2 h5 y21 ff1 fs3 fc0 sc0 lsb ws1">offering a special low-pow<span class="_ _4"></span>er mode, optimized f<span class="_ _1"></span>or chip-to-chip </div><div class="t m0 x2 h5 y22 ff1 fs3 fc0 sc0 ls19 ws1">interfaces<span class="_ _1"></span>.</div><div class="t m0 x1 h5 y23 ff1 fs3 fc0 sc0 lsc ws9">•<span class="_ _6"> </span>A user configurable analog interf<span class="_ _1"></span>ace (XADC), incor<span class="_ _2"></span>porating dual </div><div class="t m0 x2 h5 y24 ff1 fs3 fc0 sc0 lsf wsc">12-bit 1MSPS analog-to-digital conv<span class="_ _1"></span>er<span class="_ _2"></span>ters with on-chip ther<span class="_ _2"></span>mal and </div><div class="t m0 x2 h5 y25 ff1 fs3 fc0 sc0 ls14 ws11">supply sensors.</div><div class="t m0 x1 h5 y26 ff1 fs3 fc0 sc0 lsf ws1c">•<span class="_ _6"> </span>DSP slices with 25<span class="_"> </span>x<span class="_ _7"> </span>18 multiplier<span class="_ _1"></span><span class="lsc ws1d">, 48-bit accumulator<span class="_ _1"></span>, and <span class="_ _2"></span>pre-adder </span></div><div class="t m0 x2 h5 y27 ff1 fs3 fc0 sc0 lsc ws9">for high perf<span class="_ _1"></span>or<span class="_ _2"></span>mance filtering,<span class="ls1a ws1e"> including optimized symmetric </span></div><div class="t m0 x2 h5 y28 ff1 fs3 fc0 sc0 ls14 ws11">coefficient filtering.</div><div class="t m0 x3 h5 y29 ff1 fs3 fc0 sc0 ls9 ws7">•<span class="_ _6"> </span>P<span class="_ _1"></span>owerful clock management tiles (CMT), combining phase-lock<span class="_ _1"></span>ed </div><div class="t m0 x4 h5 y2a ff1 fs3 fc0 sc0 ls9 ws7">loop (PLL) and mix<span class="_ _4"></span>ed-mode clock m<span class="lsa ws8">anager (MMCM) bloc<span class="_ _1"></span>ks for high </span></div><div class="t m0 x4 h5 y2b ff1 fs3 fc0 sc0 ls14 ws11">precision and low jitter<span class="_ _1"></span>.</div><div class="t m0 x3 h5 y2c ff1 fs3 fc0 sc0 ls13 ws10">•<span class="_ _6"> </span>Integrated b<span class="_ _4"></span>lock f<span class="_ _1"></span>or PCI<span class="_"> </span>Express® (PCIe), for up to x8 Gen3 </div><div class="t m0 x4 h5 y2d ff1 fs3 fc0 sc0 ls11 wse">Endpoint and Root P<span class="_ _1"></span>or<span class="_ _2"></span>t design<span class="_ _2"></span>s.</div><div class="t m0 x3 h5 y2e ff1 fs3 fc0 sc0 ls13 ws10">•<span class="_ _6"> </span>Wide variety of configuration options, including suppor<span class="_ _2"></span>t f<span class="_ _4"></span>or </div><div class="t m0 x4 h5 y2f ff1 fs3 fc0 sc0 ls11 wse">commodity memories, 256-bit AES encr<span class="_ _2"></span>yption with HMAC/SHA-256 </div><div class="t m0 x4 h5 y30 ff1 fs3 fc0 sc0 ls11 wse">authentication, and built-in SEU detection and correction.</div><div class="t m0 x3 h5 y21 ff1 fs3 fc0 sc0 lsc ws9">•<span class="_ _6"> </span>Low-cost, wire-bond, lidless flip-chi<span class="ls13 ws10">p<span class="_ _1"></span>, and <span class="_ _2"></span>high signal integrity flip-</span></div><div class="t m0 x4 h5 y22 ff1 fs3 fc0 sc0 ls13 ws10">chip packaging off<span class="_ _1"></span>er<span class="_ _2"></span>ing easy migration between f<span class="_ _4"></span>amily members in </div><div class="t m0 x4 h5 y31 ff1 fs3 fc0 sc0 ls11 wse">the same package<span class="_ _4"></span>. All packages av<span class="_ _1"></span>ailable in Pb-free and selected </div><div class="t m0 x4 h5 y32 ff1 fs3 fc0 sc0 ls10 wsd">packages in Pb option.</div><div class="t m0 x3 h5 y25 ff1 fs3 fc0 sc0 lsb ws1">•<span class="_ _6"> </span>Designed for high perf<span class="_ _1"></span>or<span class="_ _2"></span>mance and lowest power with 28<span class="_"> </span>nm, </div><div class="t m0 x4 h5 y33 ff1 fs3 fc0 sc0 lsa ws8">HKMG, HPL process, 1.0V core<span class="lsc ws9"> voltage process technology and </span></div><div class="t m0 x4 h5 y34 ff1 fs3 fc0 sc0 ls10 wsd">0.9V core voltage option f<span class="_ _1"></span>or even lo<span class="_ _1"></span>wer power<span class="_ _1"></span>.</div><div class="t m0 x5 h6 y35 ff1 fs4 fc3 sc0 ls1b ws1">16</div><div class="t m0 x6 h7 y36 ff2 fs5 fc0 sc0 ls1c ws1f">7<span class="_"> </span>Series FPGAs Overview</div><div class="t m0 x1 h6 y37 ff1 fs4 fc0 sc0 ls1d ws20">DS180 (v1.13) No<span class="_ _1"></span>vember 30, 2012<span class="_ _9"> </span><span class="ff2 ls1e ws21">Advance Product <span class="_ _4"></span>Specificat<span class="_ _4"></span>ion</span></div><div class="t m0 x1 h6 y38 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 1<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls1e ws23">7<span class="_"> </span>Series F<span class="_ _1"></span>amilies Comparison</span></div><div class="t m0 x7 h8 y39 ff2 fs6 fc0 sc0 ls20 ws24">Maximum Capability<span class="_ _c"> </span>Artix-7 Family<span class="_ _d"> </span>Kintex-7 Famil<span class="_ _1"></span>y<span class="_ _e"> </span>Virtex-7 Family</div><div class="t m0 x8 h5 y3a ff1 fs3 fc0 sc0 lsa ws8">Logic Cells<span class="_ _f"> </span>215K<span class="_ _10"> </span>478K<span class="_ _11"> </span>1,955K</div><div class="t m0 x8 h5 y3b ff1 fs3 fc0 sc0 ls21 ws25">Block RAM</div><div class="t m0 x9 h9 y3c ff1 fs7 fc1 sc0 ls22 ws1">(1)</div><div class="t m0 xa h5 y3d ff1 fs3 fc0 sc0 lsd ws26"> 13<span class="_ _7"> </span>Mb<span class="_ _12"> </span>34<span class="_ _7"> </span>Mb<span class="_ _13"> </span>68<span class="_ _7"> </span>Mb</div><div class="t m0 x8 h5 y3e ff1 fs3 fc0 sc0 lsf wsc">DSP Slices <span class="_ _14"> </span>740<span class="_ _15"> </span>1,920<span class="_ _16"> </span>3,600</div><div class="t m0 x8 h5 y3f ff1 fs3 fc0 sc0 lsc ws9">P<span class="_ _1"></span>eak DSP P<span class="_ _4"></span>erformance</div><div class="t m0 xb h9 y40 ff1 fs7 fc1 sc0 ls23 ws1">(2)</div><div class="t m0 xc h5 y41 ff1 fs3 fc0 sc0 lsf ws1">929<span class="_"> </span>GMAC/s<span class="_ _17"> </span>2,845<span class="_"> </span>GMAC/s<span class="_ _18"> </span>5,335<span class="_"> </span>GMAC/s</div><div class="t m0 x8 h5 y42 ff1 fs3 fc0 sc0 ls24 ws1">T<span class="_ _5"></span>ransceiv<span class="_ _1"></span>ers<span class="_ _14"> </span>16<span class="_ _19"> </span>32<span class="_ _1a"> </span>96</div><div class="t m0 x8 h5 y43 ff1 fs3 fc0 sc0 lsd wsa">P<span class="_ _1"></span>eak T<span class="_ _5"></span>ransceiv<span class="_ _4"></span>er Speed<span class="_ _1b"> </span>6.6<span class="_"> </span>Gb/s<span class="_ _1c"> </span>12.5<span class="_"> </span>Gb/s<span class="_ _1d"> </span>28.05<span class="_"> </span>Gb/s</div><div class="t m0 x8 h5 y44 ff1 fs3 fc0 sc0 ls9 ws7">P<span class="_ _1"></span>eak Ser<span class="_ _2"></span>ial Bandwidth (Full Duplex)<span class="_ _1e"> </span>211<span class="_"> </span>Gb/s<span class="_ _1c"> </span>800<span class="_"> </span>Gb/s<span class="_ _1f"> </span>2,784<span class="_"> </span>Gb/s</div><div class="t m0 x8 h5 y45 ff1 fs3 fc0 sc0 ls9 ws9">PCIe Interface<span class="_ _20"> </span>x4 Gen2<span class="_ _21"> </span>x8 Gen2<span class="_ _22"> </span>x8 Gen3</div><div class="t m0 x8 h5 y46 ff1 fs3 fc0 sc0 ls13 ws10">Memor<span class="_ _2"></span>y Interface<span class="_ _10"> </span>1,066<span class="_"> </span>Mb/s<span class="_ _23"> </span>1,866<span class="_"> </span>Mb/s<span class="_ _1c"> </span>1,866<span class="_"> </span>Mb/s</div><div class="t m0 x8 h5 y47 ff1 fs3 fc0 sc0 ls13 ws10">I/O Pins<span class="_ _24"> </span>500<span class="_ _25"> </span>500 <span class="_ _26"> </span>1,200</div><div class="t m0 x8 h5 y48 ff1 fs3 fc0 sc0 ls13 ws10">I/O V<span class="_ _5"></span>oltage<span class="_ _27"> </span>1.2V<span class="_ _5"></span>, <span class="_ _1"></span>1.35V<span class="_ _5"></span>, <span class="_ _1"></span>1.5V<span class="_ _5"></span>, <span class="_ _4"></span>1.8V<span class="_ _5"></span>, <span class="_ _1"></span>2.5V<span class="_ _5"></span>, <span class="_ _1"></span>3.3V<span class="_ _28"> </span>1.2V<span class="_ _5"></span>, 1.35V<span class="_ _29"></span>, 1.5V<span class="_ _29"></span>, 1.8V<span class="_ _5"></span>, 2.5V<span class="_ _29"></span>, 3.3V<span class="_ _2a"> </span>1.2V<span class="_ _29"></span>, 1.35V<span class="_ _5"></span>, 1.5V<span class="_ _29"></span>, 1.8V<span class="_ _5"></span>, 2.5V<span class="_ _29"></span>, 3.3V</div><div class="t m0 x8 h5 y49 ff1 fs3 fc0 sc0 ls9 ws7">P<span class="_ _4"></span>ackage Options<span class="_ _2b"> </span>Low-Cost, Wire-Bond, Lidless </div><div class="t m0 xd h5 y4a ff1 fs3 fc0 sc0 ls25 ws1">Flip-Chip</div><div class="t m0 xe h5 y49 ff1 fs3 fc0 sc0 lsf wsc">Low-Cost, Lidless Flip-Chip and </div><div class="t m0 xf h5 y4a ff1 fs3 fc0 sc0 ls15 ws16">High-P<span class="_ _1"></span>erformance Flip-Chip</div><div class="t m0 x10 h5 y49 ff1 fs3 fc0 sc0 ls26 ws27">Highest P<span class="_ _1"></span>erformance Flip-Chip</div><div class="t m0 x11 h5 y4b ff2 fs3 fc0 sc0 ls10 ws1">Notes: </div><div class="t m0 x11 ha y4c ff1 fs8 fc0 sc0 ls27 ws28">1.<span class="_ _2c"> </span>Additional memory av<span class="_ _1"></span>ailable in the f<span class="_ _1"></span>or<span class="_ _2"></span>m of distributed RAM.</div><div class="t m0 x11 ha y4d ff1 fs8 fc0 sc0 ls28 ws29">2.<span class="_ _2c"> </span>P<span class="_ _1"></span>eak DSP perf<span class="_ _1"></span>or<span class="_ _2"></span>mance numbers are based<span class="_ _4"></span> on symmetrical filter i<span class="_ _4"></span>mplementation.</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595080/bg2.jpg"><div class="t m0 x12 h6 y4e ff2 fs4 fc0 sc0 ls29 ws2a">7<span class="_"> </span>Series FPGA<span class="_ _1"></span>s Overview</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">DS180 (v1.13) November 30, 2012<span class="_ _0"> </span><span class="fc1 ls1 ws1">www<span class="_ _1"></span>.xilinx.com</span></div><div class="t m0 x1 h2 y2 ff2 fs0 fc0 sc0 ls2 ws2">Adv<span class="_ _1"></span>a<span class="_ _2"></span>nce Product Specificatio<span class="_ _2"></span>n<span class="_ _3"> </span><span class="ff1 ls3 ws1">2</span></div><div class="t m0 x1 h4 y4f ff2 fs2 fc0 sc0 ls2a ws2b">Ar<span class="_ _2"></span>tix-7 FPGA Feature Summary</div><div class="t m0 x1 h6 y50 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 2<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls2b ws2c">Artix-7 FPGA Feature Summary by<span class="_ _4"></span> Device</span></div><div class="t m0 x13 h3 y51 ff2 fs1 fc0 sc0 ls2c ws1">Device</div><div class="t m0 x14 h3 y52 ff2 fs1 fc0 sc0 ls2d ws1">Logic </div><div class="t m0 x15 h3 y53 ff2 fs1 fc0 sc0 ls2e ws1">Cells</div><div class="t m0 x16 h3 y54 ff2 fs1 fc0 sc0 ls2f ws2d">Configurable Logic Blocks </div><div class="t m0 x17 h3 y55 ff2 fs1 fc0 sc0 ls30 ws1">(CLBs)</div><div class="t m0 x18 h3 y52 ff2 fs1 fc0 sc0 ls31 ws1">DSP48<span class="_ _4"></span>E1 </div><div class="t m0 x19 h3 y53 ff2 fs1 fc0 sc0 ls32 ws1">Slices</div><div class="t m0 x1a hb y56 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 x1b h3 y57 ff2 fs1 fc0 sc0 ls34 ws2e">Block RAM Blocks</div><div class="t m0 x1c hb y58 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x1d h3 y59 ff2 fs1 fc0 sc0 ls36 ws2f">Clock Mgmt </div><div class="t m0 x1e h3 y5a ff2 fs1 fc0 sc0 ls37 ws1">Tiles </div><div class="t m0 x1f h3 y5b ff2 fs1 fc0 sc0 ls38 ws1">(CMTs)</div><div class="t m0 x20 hb y5c ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x21 h3 y52 ff2 fs1 fc0 sc0 ls39 ws1">PCIe</div><div class="t m0 x22 hb y56 ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 x23 h3 y51 ff2 fs1 fc0 sc0 ls3a ws1">GTPs</div><div class="t m0 x24 h3 y5d ff2 fs1 fc0 sc0 ls3b ws1">XADC </div><div class="t m0 x25 h3 y51 ff2 fs1 fc0 sc0 ls2e ws1">Blocks</div><div class="t m0 x26 hb y5e ff2 fs9 fc1 sc0 ls35 ws1">(6)</div><div class="t m0 x27 h3 y52 ff2 fs1 fc0 sc0 ls3c ws30">T<span class="_ _1"></span>otal I/O </div><div class="t m0 x27 h3 y53 ff2 fs1 fc0 sc0 ls3d ws1">Banks</div><div class="t m0 x28 hb y56 ff2 fs9 fc1 sc0 ls35 ws1">(7)</div><div class="t m0 x29 h3 y5d ff2 fs1 fc0 sc0 ls7 ws1">Max </div><div class="t m0 x2a h3 y51 ff2 fs1 fc0 sc0 ls2c ws1">User </div><div class="t m0 x2a h3 y5f ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x2b hb y5e ff2 fs9 fc1 sc0 ls35 ws1">(8)</div><div class="t m0 x2c h3 y60 ff2 fs1 fc0 sc0 ls3e ws1">Slices</div><div class="t m0 x2d hb y5c ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 x2e h3 y61 ff2 fs1 fc0 sc0 ls3f ws1">Max </div><div class="t m0 x2f h3 y60 ff2 fs1 fc0 sc0 ls40 ws1">Distribute<span class="_ _4"></span>d </div><div class="t m0 x30 h3 y62 ff2 fs1 fc0 sc0 ls41 ws31">RAM (Kb)</div><div class="t m0 x31 h3 y60 ff2 fs1 fc0 sc0 ls40 ws1">18Kb<span class="_ _2d"> </span>36Kb</div><div class="t m0 x32 h3 y63 ff2 fs1 fc0 sc0 ls3f ws1">Max </div><div class="t m0 x32 h3 y64 ff2 fs1 fc0 sc0 ls42 ws1">(Kb)</div><div class="t m0 x8 h3 y65 ff1 fs1 fc0 sc0 ls43 ws1">XC7A20SL<span class="_ _2e"> </span>16,000<span class="_ _2f"> </span>2,500<span class="_ _30"> </span>208<span class="_ _30"> </span>60<span class="_ _31"> </span>60<span class="_ _32"> </span>30<span class="_ _2a"> </span>1,080<span class="_ _33"> </span>3<span class="_ _34"> </span>0<span class="_ _35"> </span>0<span class="_ _36"> </span>1<span class="_ _35"> </span>5<span class="_ _31"> </span>216</div><div class="t m0 x8 h3 y66 ff1 fs1 fc0 sc0 ls43 ws1">XC7A35SL<span class="_ _2e"> </span>32,909<span class="_ _2f"> </span>5,142<span class="_ _30"> </span>453<span class="_ _37"> </span>120<span class="_ _38"> </span>130<span class="_ _39"> </span>65<span class="_ _2a"> </span>2,340<span class="_ _33"> </span>3<span class="_ _34"> </span>0<span class="_ _35"> </span>0<span class="_ _36"> </span>1<span class="_ _3a"> </span>5<span class="_ _31"> </span>216</div><div class="t m0 x8 h3 y67 ff1 fs1 fc0 sc0 ls43 ws1">XC7A50SL<span class="_ _2e"> </span>52,480<span class="_ _2f"> </span>8,200<span class="_ _30"> </span>688<span class="_ _37"> </span>180<span class="_ _38"> </span>190<span class="_ _39"> </span>95<span class="_ _2a"> </span>3,420<span class="_ _33"> </span>4<span class="_ _34"> </span>0<span class="_ _3a"> </span>0<span class="_ _36"> </span>1<span class="_ _35"> </span>6<span class="_ _31"> </span>300</div><div class="t m0 x8 h3 y68 ff1 fs1 fc0 sc0 ls43 ws1">XC7A75SL<span class="_ _2e"> </span>71,642<span class="_ _3b"> </span>11,194<span class="_ _37"> </span>974<span class="_ _37"> </span>240<span class="_ _38"> </span>250<span class="_ _3c"> </span>125<span class="_ _3d"> </span>4,500<span class="_ _33"> </span>4<span class="_ _34"> </span>0<span class="_ _35"> </span>0<span class="_ _36"> </span>1<span class="_ _3a"> </span>6<span class="_ _31"> </span>300</div><div class="t m0 x8 h3 y69 ff1 fs1 fc0 sc0 ls43 ws1">XC7A20SL<span class="_ _5"></span>T<span class="_ _3e"> </span>16,000<span class="_ _2f"> </span>2,500<span class="_ _30"> </span>208<span class="_ _30"> </span>60<span class="_ _31"> </span>60<span class="_ _32"> </span>30<span class="_ _2a"> </span>1,080<span class="_ _33"> </span>3<span class="_ _34"> </span>1<span class="_ _35"> </span>4<span class="_ _36"> </span>1<span class="_ _3a"> </span>5<span class="_ _31"> </span>216</div><div class="t m0 x8 h3 y6a ff1 fs1 fc0 sc0 ls43 ws1">XC7A35SL<span class="_ _5"></span>T<span class="_ _3e"> </span>32,909<span class="_ _2f"> </span>5,142<span class="_ _30"> </span>453<span class="_ _37"> </span>120<span class="_ _38"> </span>130<span class="_ _39"> </span>65<span class="_ _2a"> </span>2,340<span class="_ _33"> </span>3<span class="_ _34"> </span>1<span class="_ _3a"> </span>4<span class="_ _36"> </span>1<span class="_ _35"> </span>5<span class="_ _31"> </span>216</div><div class="t m0 x8 h3 y6b ff1 fs1 fc0 sc0 ls43 ws1">XC7A50SL<span class="_ _5"></span>T<span class="_ _3e"> </span>52,480<span class="_ _2f"> </span>8,200<span class="_ _30"> </span>688<span class="_ _37"> </span>180<span class="_ _38"> </span>190<span class="_ _39"> </span>95<span class="_ _2a"> </span>3,420<span class="_ _33"> </span>4<span class="_ _34"> </span>1<span class="_ _3a"> </span>8<span class="_ _36"> </span>1<span class="_ _35"> </span>6<span class="_ _31"> </span>300</div><div class="t m0 x8 h3 y6c ff1 fs1 fc0 sc0 ls32 ws1">XC7A75SL<span class="_ _5"></span>T<span class="_ _3e"> </span>71,642<span class="_ _3b"> </span>11,194<span class="_ _37"> </span>974<span class="_ _37"> </span>240<span class="_ _38"> </span>250<span class="_ _3c"> </span>125<span class="_ _3d"> </span>4,500<span class="_ _33"> </span>4<span class="_ _34"> </span>1<span class="_ _3a"> </span>8<span class="_ _36"> </span>1<span class="_ _35"> </span>6<span class="_ _31"> </span>300</div><div class="t m0 x8 h3 y6d ff1 fs1 fc0 sc0 ls3e ws1">XC7A100T<span class="_ _3f"> </span>101,440<span class="_ _40"> </span>15,850<span class="_ _41"> </span>1,188<span class="_ _42"> </span>240<span class="_ _38"> </span>270<span class="_ _3c"> </span>135<span class="_ _3d"> </span>4,860<span class="_ _33"> </span>6<span class="_ _34"> </span>1<span class="_ _3a"> </span>8<span class="_ _36"> </span>1<span class="_ _3a"> </span>6<span class="_ _43"> </span>300</div><div class="t m0 x8 h3 y6e ff1 fs1 fc0 sc0 ls3e ws1">XC7A200T<span class="_ _3f"> </span>215,360<span class="_ _40"> </span>33,650<span class="_ _41"> </span>2,888<span class="_ _42"> </span>740<span class="_ _38"> </span>730<span class="_ _3c"> </span>365<span class="_ _44"> </span>13,140<span class="_ _3b"> </span>10<span class="_ _45"> </span>1<span class="_ _31"> </span>16<span class="_ _46"> </span>1<span class="_ _31"> </span>10<span class="_ _47"> </span>500</div><div class="t m0 x11 h3 y6f ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 y70 ff1 fs1 fc0 sc0 ls6 ws32">1.<span class="_ _28"> </span>Each 7<span class="_"> </span>series FPGA slice co<span class="_ _1"></span>ntains four LUTs and e<span class="_ _4"></span>ight flip-flops<span class="_ _1"></span><span class="ls3d ws33">; only some slices can use thei<span class="ls37 ws34">r LUTs as distrib<span class="_ _4"></span>uted RAM or SR<span class="ls3e ws1">Ls<span class="_ _4"></span>.</span></span></span></div><div class="t m0 x11 h3 y71 ff1 fs1 fc0 sc0 ls3f ws35">2.<span class="_ _28"> </span>Each DSP slice contains a pre-adde<span class="_ _4"></span>r<span class="_ _1"></span>, a 25<span class="_"> </span>x<span class="_"> </span>18 multiplier<span class="_ _1"></span>, an adder, and<span class="_ _4"></span> an accumulator<span class="_ _1"></span>.</div><div class="t m0 x11 h3 y72 ff1 fs1 fc0 sc0 ls44 ws35">3.<span class="_ _28"> </span>Block RAMs are<span class="_ _4"></span> fundamentally 36<span class="_"> </span>Kb in size; each b<span class="_ _1"></span>lock can also be used as two independe<span class="_ _4"></span>nt 18<span class="_"> </span>Kb bloc<span class="_ _1"></span>ks.</div><div class="t m0 x11 h3 y73 ff1 fs1 fc0 sc0 ls44 ws35">4.<span class="_ _28"> </span>Each CMT contains one MMCM and one PLL.</div><div class="t m0 x11 h3 y74 ff1 fs1 fc0 sc0 ls5 ws4">5.<span class="_ _28"> </span>Artix-7 FPGA Interface Bloc<span class="_ _1"></span>ks for PCI Express support up to x4 Gen 2.</div><div class="t m0 x11 h3 y75 ff1 fs1 fc0 sc0 ls4 ws3">6.<span class="_ _28"> </span>Artix-7 SL/SL<span class="_ _5"></span>T devices ha<span class="_ _1"></span>ve enhanced analog functionality<span class="_ _29"></span>.</div><div class="t m0 x11 h3 y76 ff1 fs1 fc0 sc0 ls6 ws32">7.<span class="_ _28"> </span>Does not include con<span class="_ _1"></span>f<span class="_ _2"></span>iguration<span class="_ _4"></span> Bank 0.</div><div class="t m0 x11 h3 y77 ff1 fs1 fc0 sc0 ls6 ws36">8.<span class="_ _28"> </span>This number does not include GTP<span class="_ _8"></span>, GTX, or GTH transceiv<span class="_ _4"></span>ers.</div><div class="t m0 x1 h6 y78 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 3<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls45 ws37">Artix-7 FPGA Device-P<span class="_ _1"></span>acka<span class="_ _1"></span>g<span class="_ _2"></span>e Combinations and<span class="_ _4"></span> Maximu<span class="_ _4"></span>m I/Os</span></div><div class="t m0 x8 h3 y79 ff2 fs1 fc0 sc0 ls46 ws1">Package</div><div class="t m0 x33 hb y7a ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 x34 h3 y79 ff2 fs1 fc0 sc0 ls4 ws1">CPG236<span class="_ _48"> </span>CSG325<span class="_ _48"> </span>CSG484<span class="_ _48"> </span>CPG237<span class="_ _48"> </span>CSG326<span class="_ _48"> </span>CSG485<span class="_ _48"> </span>FGG677</div><div class="t m0 x8 h3 y7b ff2 fs1 fc0 sc0 ls47 ws38">Size (mm)<span class="_ _49"> </span>10 x 10<span class="_ _4a"> </span>15 x 15<span class="_ _4a"> </span>19 x 19<span class="_ _4a"> </span>10 x 10<span class="_ _4a"> </span>15 x 15<span class="_ _4a"> </span>19 x 19<span class="_ _4a"> </span>27 x 27</div><div class="t m0 x8 h3 y7c ff2 fs1 fc0 sc0 ls48 ws39">Ball Pitch (mm)<span class="_ _30"> </span>0.5<span class="_ _4b"> </span>0.8<span class="_ _4b"> </span>0.8<span class="_ _4b"> </span>0.5<span class="_ _4b"> </span>0.8<span class="_ _4c"> </span>0.8<span class="_ _4b"> </span>1.0</div><div class="t m0 x8 h3 y7d ff2 fs1 fc0 sc0 ls6 ws1">Device<span class="_ _4d"> </span>GTP</div><div class="t m0 x35 h3 y7e ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x36 h3 y7d ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x37 h3 y7e ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x38 h3 y7d ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x39 h3 y7e ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x3a h3 y7d ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x3b h3 y7e ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x3c h3 y7d ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x3d h3 y7e ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x3e h3 y7d ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x25 h3 y7e ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x3f h3 y7d ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x40 h3 y7e ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x41 h3 y7f ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x42 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x43 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HD</div><div class="t m0 x44 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x45 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x46 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x47 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HD</div><div class="t m0 xd hb y80 ff2 fs9 fc1 sc0 ls33 ws1">(3)</div><div class="t m0 x48 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x49 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x4a h3 y81 ff2 fs1 fc0 sc0 ls31 ws1">HD</div><div class="t m0 x4b hb y80 ff2 fs9 fc1 sc0 ls33 ws1">(3)</div><div class="t m0 x4c h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x4d hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x4e h3 y81 ff2 fs1 fc0 sc0 ls31 ws1">HD</div><div class="t m0 x4f hb y80 ff2 fs9 fc1 sc0 ls33 ws1">(3)</div><div class="t m0 x50 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x51 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x52 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HD</div><div class="t m0 x22 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x53 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x54 hb y80 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 x55 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HD</div><div class="t m0 x56 hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x57 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x58 hb y80 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 x59 h3 y81 ff2 fs1 fc0 sc0 ls36 ws1">HD</div><div class="t m0 x2b hb y80 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x8 h3 y82 ff1 fs1 fc0 sc0 ls3e ws1">XC7A20SL<span class="_ _4e"> </span>0<span class="_ _4f"> </span>48<span class="_ _6"> </span>52<span class="_ _3d"> </span>0<span class="_ _6"> </span>108<span class="_ _50"> </span>108</div><div class="t m0 x8 h3 y83 ff1 fs1 fc0 sc0 ls3e ws1">XC7A35SL<span class="_ _4e"> </span>0<span class="_ _4f"> </span>48<span class="_ _6"> </span>52<span class="_ _3d"> </span>0<span class="_ _6"> </span>108<span class="_ _50"> </span>108</div><div class="t m0 x8 h3 y84 ff1 fs1 fc0 sc0 ls3e ws1">XC7A50SL<span class="_ _51"> </span>0<span class="_ _6"> </span>144<span class="_ _2c"> </span>156</div><div class="t m0 x8 h3 y85 ff1 fs1 fc0 sc0 ls3e ws1">XC7A75SL<span class="_ _51"> </span>0<span class="_ _6"> </span>144<span class="_ _2c"> </span>156</div><div class="t m0 x8 h3 y86 ff1 fs1 fc0 sc0 ls3e ws1">XC7A20SL<span class="_ _5"></span>T<span class="_ _52"> </span>1<span class="_ _4f"> </span>48<span class="_ _6"> </span>52<span class="_ _3d"> </span>4<span class="_ _6"> </span>108<span class="_ _53"> </span>77<span class="_ _4f"> </span>4<span class="_ _6"> </span>108<span class="_ _2c"> </span>108</div><div class="t m0 x8 h3 y87 ff1 fs1 fc0 sc0 ls3e ws1">XC7A35SL<span class="_ _5"></span>T<span class="_ _52"> </span>1<span class="_ _4f"> </span>48<span class="_ _6"> </span>52<span class="_ _3d"> </span>4<span class="_ _6"> </span>108<span class="_ _53"> </span>77<span class="_ _4f"> </span>4<span class="_ _6"> </span>108<span class="_ _2c"> </span>108</div><div class="t m0 x8 h3 y88 ff1 fs1 fc0 sc0 ls3e ws1">XC7A50SL<span class="_ _5"></span>T<span class="_ _54"> </span>4<span class="_ _6"> </span>108<span class="_ _53"> </span>77<span class="_ _3d"> </span>6<span class="_ _6"> </span>126<span class="_ _50"> </span>108<span class="_ _6"> </span>8<span class="_ _55"> </span>144<span class="_ _50"> </span>156</div><div class="t m0 x8 h3 y89 ff1 fs1 fc0 sc0 ls3e ws1">XC7A75SL<span class="_ _5"></span>T</div><div class="t m0 x5a h3 y8a ff1 fs1 fc0 sc0 ls3e ws1">4<span class="_ _55"> </span>108<span class="_ _53"> </span>77<span class="_ _4f"> </span>6<span class="_ _6"> </span>126<span class="_ _50"> </span>108<span class="_ _55"> </span>8<span class="_ _6"> </span>144<span class="_ _50"> </span>156</div><div class="t m0 x11 h3 y8b ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 y8c ff1 fs1 fc0 sc0 ls5 ws4">1.<span class="_ _28"> </span>All packages liste<span class="_ _4"></span>d in this tabl<span class="_ _4"></span>e are Pb-free.</div><div class="t m0 x11 h3 y8d ff1 fs1 fc0 sc0 ls3e ws3a">2.<span class="_ _28"> </span>HR = High Range <span class="_ _4"></span>I/O with su<span class="_ _4"></span>pport for I/O v<span class="_ _1"></span>oltage from 1.2V to <span class="_ _4"></span>3.3V<span class="_ _29"></span>.</div><div class="t m0 x11 h3 y8e ff1 fs1 fc0 sc0 ls4a ws3b">3.<span class="_ _28"> </span>HD = High Density I/O<span class="_ _1"></span>.</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595080/bg3.jpg"><div class="t m0 x12 h6 y4e ff2 fs4 fc0 sc0 ls29 ws2a">7<span class="_"> </span>Series FPGA<span class="_ _1"></span>s Overview</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">DS180 (v1.13) November 30, 2012<span class="_ _0"> </span><span class="fc1 ls1 ws1">www<span class="_ _1"></span>.xilinx.com</span></div><div class="t m0 x1 h2 y2 ff2 fs0 fc0 sc0 ls2 ws2">Adv<span class="_ _1"></span>a<span class="_ _2"></span>nce Product Specificatio<span class="_ _2"></span>n<span class="_ _3"> </span><span class="ff1 ls3 ws1">3</span></div><div class="t m0 x1 h4 y8f ff2 fs2 fc0 sc0 ls4b ws3c">Kintex-7 FPGA Feat<span class="_ _4"></span>ure Summary</div><div class="t m0 x1 h6 y90 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 4<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls4c ws3d">Artix-7 FPGA Device-P<span class="_ _1"></span>acka<span class="_ _1"></span>g<span class="_ _2"></span>e Combinations and Maxi<span class="_ _4"></span>mu<span class="_ _4"></span>m I/Os - Continu<span class="_ _1"></span>e<span class="_ _2"></span>d</span></div><div class="t m0 x8 h3 y91 ff2 fs1 fc0 sc0 ls46 ws1">Package</div><div class="t m0 x33 hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 x5b h3 y91 ff2 fs1 fc0 sc0 ls37 ws1">CSG324<span class="_ _2f"> </span>FTG256<span class="_ _56"> </span>SBG484<span class="_ _2e"> </span>FGG484</div><div class="t m0 x5c hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x5d h3 y91 ff2 fs1 fc0 sc0 ls3d ws1">FBG484</div><div class="t m0 x5e hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x1f h3 y91 ff2 fs1 fc0 sc0 ls4d ws1">FGG676</div><div class="t m0 x51 hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x5f h3 y91 ff2 fs1 fc0 sc0 ls3e ws1">FBG676</div><div class="t m0 x60 hb y92 ff2 fs9 fc1 sc0 ls33 ws1">(3)</div><div class="t m0 x61 h3 y91 ff2 fs1 fc0 sc0 ls3d ws1">FFG1156</div><div class="t m0 x8 h3 y93 ff2 fs1 fc0 sc0 ls32 ws3e">Size (mm)<span class="_ _48"> </span>15 x 15<span class="_ _42"> </span>17<span class="_ _4"></span> x 17<span class="_ _35"> </span>19 x 19<span class="_ _42"> </span>23 x 23<span class="_ _3a"> </span>23 x 23<span class="_ _42"> </span>27 x 27<span class="_ _35"> </span>27 x 27<span class="_ _35"> </span>35 x 35</div><div class="t m0 x8 h3 y94 ff2 fs1 fc0 sc0 ls4e ws3f">Ball Pitch (mm)<span class="_ _4e"> </span>0.8<span class="_ _57"> </span>1.0<span class="_ _57"> </span>0.8<span class="_ _57"> </span>1.0<span class="_ _58"> </span>1.0<span class="_ _58"> </span>1.0<span class="_ _57"> </span>1.0<span class="_ _58"> </span>1.0</div><div class="t m0 x8 h3 y95 ff2 fs1 fc0 sc0 ls6 ws1">Device<span class="_ _59"> </span>GTP</div><div class="t m0 x62 h3 y96 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x63 h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x64 h3 y96 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x65 h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x66 h3 y96 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x67 h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x68 h3 y96 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x69 h3 y95 ff2 fs1 fc0 sc0 ls3c ws1">GTP</div><div class="t m0 x6a h3 y96 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x6b h3 y95 ff2 fs1 fc0 sc0 ls4f ws1">GTP</div><div class="t m0 x6c h3 y96 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x52 h3 y95 ff2 fs1 fc0 sc0 ls4f ws1">GTP</div><div class="t m0 x10 h3 y96 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x6d h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">GTP</div><div class="t m0 x6e h3 y96 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x6f h3 y97 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x2c hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x70 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x5 hb y98 ff2 fs9 fc1 sc0 ls33 ws1">(4)</div><div class="t m0 x71 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x72 hb y98 ff2 fs9 fc1 sc0 ls33 ws1">(4)</div><div class="t m0 x73 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x74 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x75 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x76 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x77 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x78 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x79 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x7a hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x7b h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 x27 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x8 h3 y9a ff1 fs1 fc0 sc0 ls4 ws1">XC7A100T<span class="_ _5a"> </span>0<span class="_ _2a"> </span>210<span class="_ _2a"> </span>0<span class="_ _2a"> </span>170<span class="_ _5b"> </span><span class="ls3e">4<span class="_ _2a"> </span>285<span class="_ _5b"> </span><span class="ls50">83<span class="_ _5c"></span>0<span class="_ _5c"></span>0</span></span></div><div class="t m0 x8 h3 y9b ff1 fs1 fc0 sc0 ls4 ws1">XC7A200T<span class="_ _5d"> </span><span class="ls3e">4<span class="_ _2a"> </span>285<span class="_ _5b"> </span><span class="ls50">42<span class="_ _5c"></span>8<span class="_ _5c"></span>5<span class="_ _5e"> </span><span class="ls3e">8<span class="_ _2a"> </span>400<span class="_ _3d"> </span>16<span class="_ _4f"> </span>500</span></span></span></div><div class="t m0 x11 h3 y9c ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 y9d ff1 fs1 fc0 sc0 ls5 ws4">1.<span class="_ _28"> </span>All packages liste<span class="_ _4"></span>d are Pb-free. Some<span class="_ _4"></span> packages are a<span class="_ _1"></span>vailable in Pb option.</div><div class="t m0 x11 h3 y9e ff1 fs1 fc0 sc0 ls51 ws40">2.<span class="_ _28"> </span>Devices in<span class="_ _1"></span> FGG484 and FBG484 are f<span class="_ _1"></span>ootpr<span class="_ _2"></span>int compatib<span class="_ _1"></span>le. </div><div class="t m0 x11 h3 y9f ff1 fs1 fc0 sc0 ls51 ws40">3.<span class="_ _28"> </span>Devices in<span class="_ _1"></span> FGG676 and FBG676 are f<span class="_ _1"></span>ootpr<span class="_ _2"></span>int compatib<span class="_ _1"></span>le.</div><div class="t m0 x11 h3 ya0 ff1 fs1 fc0 sc0 ls3e ws41">4.<span class="_ _28"> </span>HR = High Range I/O with support for I/O v<span class="_ _1"></span>oltage from 1.2V to 3.3V<span class="_ _29"></span>.</div><div class="t m0 x1 h6 ya1 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 5<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls52 ws42">Kintex-7 FPGA Fe<span class="_ _4"></span>ature Summary by De<span class="_ _1"></span>vice</span></div><div class="t m0 x7c h3 ya2 ff2 fs1 fc0 sc0 ls46 ws1">Device</div><div class="t m0 x7d h3 ya3 ff2 fs1 fc0 sc0 ls53 ws1">Logic </div><div class="t m0 x7e h3 ya4 ff2 fs1 fc0 sc0 ls41 ws1">Cells</div><div class="t m0 x7f h3 ya5 ff2 fs1 fc0 sc0 ls54 ws43">Configurable Logic </div><div class="t m0 x80 h3 ya6 ff2 fs1 fc0 sc0 ls55 ws44">Blocks (CLBs)</div><div class="t m0 x38 h3 ya3 ff2 fs1 fc0 sc0 ls32 ws1">DSP </div><div class="t m0 x81 h3 ya4 ff2 fs1 fc0 sc0 ls32 ws1">Slices</div><div class="t m0 x82 hb ya7 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 x1b h3 ya8 ff2 fs1 fc0 sc0 ls42 ws45">Block RAM Blocks</div><div class="t m0 x1c hb ya9 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x83 h3 ya2 ff2 fs1 fc0 sc0 ls42 ws1">CMTs</div><div class="t m0 x84 hb yaa ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x85 h3 ya2 ff2 fs1 fc0 sc0 ls39 ws1">PCIe</div><div class="t m0 x86 hb yaa ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 x10 h3 ya2 ff2 fs1 fc0 sc0 ls56 ws1">GTXs</div><div class="t m0 x24 h3 ya3 ff2 fs1 fc0 sc0 ls36 ws1">XADC </div><div class="t m0 x25 h3 ya4 ff2 fs1 fc0 sc0 ls57 ws1">Blocks</div><div class="t m0 x87 h3 ya3 ff2 fs1 fc0 sc0 ls58 ws46">T<span class="_ _5"></span>otal I/O </div><div class="t m0 x87 h3 ya4 ff2 fs1 fc0 sc0 ls36 ws1">Banks</div><div class="t m0 x88 hb ya7 ff2 fs9 fc1 sc0 ls35 ws1">(6)</div><div class="t m0 x89 h3 yab ff2 fs1 fc0 sc0 ls7 ws1">Max </div><div class="t m0 x29 h3 yac ff2 fs1 fc0 sc0 ls7 ws1">User </div><div class="t m0 x29 h3 yad ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x8a hb yae ff2 fs9 fc1 sc0 ls33 ws1">(7)</div><div class="t m0 x2c h3 yaf ff2 fs1 fc0 sc0 ls59 ws1">Slices</div><div class="t m0 x2d hb yb0 ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 x45 h3 ya4 ff2 fs1 fc0 sc0 ls7 ws1">Max </div><div class="t m0 x70 h3 yb1 ff2 fs1 fc0 sc0 ls5a ws1">Distributed </div><div class="t m0 x2f h3 yb2 ff2 fs1 fc0 sc0 ls53 ws47">RAM (Kb)</div><div class="t m0 x8b h3 yb1 ff2 fs1 fc0 sc0 ls5b ws48">18<span class="_"> </span>Kb<span class="_ _2d"> </span>36<span class="_"> </span>Kb<span class="_ _2c"> </span>Max (Kb)</div><div class="t m0 x13 h3 yb3 ff1 fs1 fc0 sc0 ls3e ws1">XC7K70T<span class="_ _5f"> </span>65,600<span class="_ _3c"> </span>10,250<span class="_ _60"> </span>838<span class="_ _61"> </span>240<span class="_ _32"> </span>270<span class="_ _39"> </span>135<span class="_ _62"> </span>4,860<span class="_ _56"> </span>6<span class="_ _5a"> </span>1<span class="_ _63"> </span>8<span class="_ _2f"> </span>1<span class="_ _63"> </span>6<span class="_ _56"> </span>300</div><div class="t m0 x8c h3 yb4 ff1 fs1 fc0 sc0 ls3e ws1">XC7K160T<span class="_ _64"> </span>162,240<span class="_ _64"> </span>25,350<span class="_ _31"> </span>2,188<span class="_ _35"> </span>600<span class="_ _32"> </span>650<span class="_ _39"> </span>325<span class="_ _2a"> </span>11,700<span class="_ _65"> </span>8<span class="_ _5a"> </span>1<span class="_ _4e"> </span>8<span class="_ _2f"> </span>1<span class="_ _66"> </span>8<span class="_ _56"> </span>400</div><div class="t m0 x8c h3 yb5 ff1 fs1 fc0 sc0 ls3e ws1">XC7K325T<span class="_ _64"> </span>326,080<span class="_ _64"> </span>50,950<span class="_ _31"> </span>4,000<span class="_ _35"> </span>840<span class="_ _32"> </span>890<span class="_ _39"> </span>445<span class="_ _2a"> </span>16,020<span class="_ _2e"> </span>10<span class="_ _67"> </span>1<span class="_ _35"> </span>16<span class="_ _3b"> </span>1<span class="_ _35"> </span>10<span class="_ _65"> </span>500</div><div class="t m0 x8c h3 yb6 ff1 fs1 fc0 sc0 ls5c ws1">XC7K355T<span class="_ _64"> </span>356,160<span class="_ _64"> </span>55,650<span class="_ _31"> </span>5,088<span class="_ _56"> </span>1,440<span class="_ _68"> </span>1,430<span class="_ _69"> </span>715<span class="_ _69"> </span>25,740<span class="_ _65"> </span>6<span class="_ _5a"> </span>1<span class="_ _35"> </span>24<span class="_ _3b"> </span>1<span class="_ _66"> </span>6<span class="_ _56"> </span>300</div><div class="t m0 x8c h3 yb7 ff1 fs1 fc0 sc0 ls5c ws1">XC7K410T<span class="_ _64"> </span>406,720<span class="_ _68"> </span>63,550<span class="_ _43"> </span>5,663<span class="_ _56"> </span>1,540<span class="_ _68"> </span>1,590<span class="_ _69"> </span>795<span class="_ _69"> </span>28,620<span class="_ _40"> </span>10<span class="_ _6a"> </span>1<span class="_ _35"> </span>16<span class="_ _3b"> </span>1<span class="_ _35"> </span>10<span class="_ _65"> </span>500</div><div class="t m0 x8c h3 yb8 ff1 fs1 fc0 sc0 ls5c ws1">XC7K420T<span class="_ _64"> </span>416,960<span class="_ _68"> </span>65,150<span class="_ _43"> </span>5,938<span class="_ _56"> </span>1,680<span class="_ _68"> </span>1,670<span class="_ _69"> </span>835<span class="_ _69"> </span>30,060<span class="_ _65"> </span>8<span class="_ _5a"> </span>1<span class="_ _6b"> </span>32<span class="_ _3b"> </span>1<span class="_ _63"> </span>8<span class="_ _56"> </span>400</div><div class="t m0 x8c h3 yb9 ff1 fs1 fc0 sc0 ls5c ws1">XC7K480T<span class="_ _64"> </span>477,760<span class="_ _68"> </span>74,650<span class="_ _43"> </span>6,788<span class="_ _56"> </span>1,920<span class="_ _68"> </span>1,910<span class="_ _69"> </span>955<span class="_ _69"> </span>34,380<span class="_ _65"> </span>8<span class="_ _5a"> </span>1<span class="_ _6b"> </span>32<span class="_ _3b"> </span>1<span class="_ _63"> </span>8<span class="_ _56"> </span>400</div><div class="t m0 x11 h3 yba ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 ybb ff1 fs1 fc0 sc0 ls6 ws32">1.<span class="_ _28"> </span>Each 7<span class="_"> </span>series FPGA slice co<span class="_ _1"></span>ntains four LUTs and e<span class="_ _4"></span>ight flip-flops<span class="_ _1"></span><span class="ls3d ws33">; only some slices can use thei<span class="ls37 ws34">r LUTs as distrib<span class="_ _4"></span>uted RAM or SR<span class="ls3e ws1">Ls<span class="_ _4"></span>.</span></span></span></div><div class="t m0 x11 h3 ybc ff1 fs1 fc0 sc0 ls3f ws35">2.<span class="_ _28"> </span>Each DSP slice contains a pre-adde<span class="_ _4"></span>r<span class="_ _1"></span>, a 25<span class="_"> </span>x<span class="_"> </span>18 multiplier<span class="_ _1"></span>, an adder, and<span class="_ _4"></span> an accumulator<span class="_ _1"></span>.</div><div class="t m0 x11 h3 ybd ff1 fs1 fc0 sc0 ls44 ws35">3.<span class="_ _28"> </span>Block RAMs are<span class="_ _4"></span> fundamentally 36<span class="_"> </span>Kb in size; each b<span class="_ _1"></span>lock can also be used as two independe<span class="_ _4"></span>nt 18 Kb bloc<span class="_ _1"></span>ks.</div><div class="t m0 x11 h3 ybe ff1 fs1 fc0 sc0 ls44 ws35">4.<span class="_ _28"> </span>Each CMT contains one MMCM and one PLL.</div><div class="t m0 x11 h3 ybf ff1 fs1 fc0 sc0 ls6 ws49">5.<span class="_ _28"> </span>Kinte<span class="_ _4"></span>x-7 FPGA Interf<span class="_ _1"></span>ace Blocks for PCI Express suppo<span class="_ _4"></span>r<span class="_ _2"></span>t up to x8 Gen 2.</div><div class="t m0 x11 h3 yc0 ff1 fs1 fc0 sc0 ls6 ws32">6.<span class="_ _28"> </span>Does not include con<span class="_ _1"></span>f<span class="_ _2"></span>iguration<span class="_ _4"></span> Bank 0.</div><div class="t m0 x11 h3 yc1 ff1 fs1 fc0 sc0 ls6 ws36">7.<span class="_ _28"> </span>This number does not include GTP<span class="_ _8"></span>, GTX, or GTH transceiv<span class="_ _4"></span>ers.</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595080/bg4.jpg"><div class="t m0 x12 h6 y4e ff2 fs4 fc0 sc0 ls29 ws2a">7<span class="_"> </span>Series FPGA<span class="_ _1"></span>s Overview</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">DS180 (v1.13) November 30, 2012<span class="_ _0"> </span><span class="fc1 ls1 ws1">www<span class="_ _1"></span>.xilinx.com</span></div><div class="t m0 x1 h2 y2 ff2 fs0 fc0 sc0 ls2 ws2">Adv<span class="_ _1"></span>a<span class="_ _2"></span>nce Product Specificatio<span class="_ _2"></span>n<span class="_ _3"> </span><span class="ff1 ls3 ws1">4</span></div><div class="t m0 x1 h4 yc2 ff2 fs2 fc0 sc0 ls4b ws3c">Vir<span class="_ _2"></span>te<span class="_ _4"></span>x-7 FPGA Feature Summary</div><div class="t m0 x1 h6 y90 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 6<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls5d ws4a">Kintex-7 FPGA Device-P<span class="_ _1"></span>ackage Combinations and Maximum I/Os</span></div><div class="t m0 x8d h3 y91 ff2 fs1 fc0 sc0 ls46 ws1">Package</div><div class="t m0 x8e hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 x8f h3 y91 ff2 fs1 fc0 sc0 ls7 ws1">FBG484<span class="_ _6c"> </span>FBG676</div><div class="t m0 x90 hb y92 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 x91 h3 y91 ff2 fs1 fc0 sc0 ls2e ws1">FFG676</div><div class="t m0 x92 hb y92 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 xf h3 y91 ff2 fs1 fc0 sc0 ls3d ws1">FBG900</div><div class="t m0 x93 hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x94 h3 y91 ff2 fs1 fc0 sc0 ls34 ws1">FFG900</div><div class="t m0 x95 hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x96 h3 y91 ff2 fs1 fc0 sc0 ls5b ws1">FFG901<span class="_ _48"> </span>FFG1156</div><div class="t m0 x97 h3 y93 ff2 fs1 fc0 sc0 ls32 ws3e">Size (mm)<span class="_ _6d"> </span>23 x 23<span class="_ _49"> </span>27 x 27<span class="_ _6e"> </span>27 x 27<span class="_ _6e"> </span>31 x 31<span class="_ _6f"> </span>31 x 31<span class="_ _6f"> </span>31 x 31<span class="_ _49"> </span>35 x 35</div><div class="t m0 x8c h3 y94 ff2 fs1 fc0 sc0 ls5e ws4b">Ball Pitch </div><div class="t m0 x2 h3 yc3 ff2 fs1 fc0 sc0 ls2e ws1">(mm)</div><div class="t m0 x98 h3 yc4 ff2 fs1 fc0 sc0 ls5f ws1">1.0<span class="_ _70"> </span>1.0<span class="_ _71"> </span>1.0<span class="_ _72"> </span>1.0<span class="_ _70"> </span>1.0<span class="_ _71"> </span>1.0<span class="_ _70"> </span>1.0</div><div class="t m0 x99 h3 yc5 ff2 fs1 fc0 sc0 ls40 ws1">Device<span class="_ _3c"> </span>GTX</div><div class="t m0 x9a h3 y95 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x9b h3 yc5 ff2 fs1 fc0 sc0 ls4f ws1">GTX</div><div class="t m0 x9c h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x18 h3 yc5 ff2 fs1 fc0 sc0 ls49 ws1">GTX</div><div class="t m0 x8b h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x9d h3 yc5 ff2 fs1 fc0 sc0 ls49 ws1">GTX</div><div class="t m0 x9e h3 y95 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x83 h3 yc5 ff2 fs1 fc0 sc0 ls49 ws1">GTX</div><div class="t m0 x9f h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 xa0 h3 yc5 ff2 fs1 fc0 sc0 ls49 ws1">GTX</div><div class="t m0 x25 h3 y95 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x3f h3 yc5 ff2 fs1 fc0 sc0 ls49 ws1">GTX</div><div class="t m0 x40 h3 y95 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 xa1 h3 yc6 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xa2 hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xa3 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x44 hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 x2f h3 yc8 ff2 fs1 fc0 sc0 ls31 ws1">HR</div><div class="t m0 x46 hb yc7 ff2 fs9 fc1 sc0 ls33 ws1">(4)</div><div class="t m0 xa4 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xd hb yc7 ff2 fs9 fc1 sc0 ls33 ws1">(5)</div><div class="t m0 x1a h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xa5 hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xa6 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x73 hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xa7 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xa8 hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xa9 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xaa hb yc7 ff2 fs9 fc1 sc0 ls33 ws1">(5)</div><div class="t m0 x77 h3 yc8 ff2 fs1 fc0 sc0 ls31 ws1">HR</div><div class="t m0 x78 hb yc7 ff2 fs9 fc1 sc0 ls33 ws1">(4)</div><div class="t m0 xab h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xac hb yc7 ff2 fs9 fc1 sc0 ls33 ws1">(5)</div><div class="t m0 xad h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xae hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x26 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xaf hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 x88 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xb0 hb yc7 ff2 fs9 fc1 sc0 ls60 ws1">(4)</div><div class="t m0 xb1 h3 yc8 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xb2 hb yc7 ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 x8c h3 yc9 ff1 fs1 fc0 sc0 ls4 ws1">XC7K70T<span class="_ _39"> </span>4<span class="_ _6"> </span>185<span class="_ _50"> </span>100<span class="_ _73"> </span>8<span class="_ _6"> </span>200<span class="_ _74"> </span>100</div><div class="t m0 x8d h3 yca ff1 fs1 fc0 sc0 ls43 ws1">XC7K160T<span class="_ _75"> </span>4<span class="_ _6"> </span>185<span class="_ _74"> </span>100<span class="_ _6"> </span>8<span class="_ _6"> </span>250<span class="_ _74"> </span>150<span class="_ _73"> </span>8<span class="_ _73"> </span>250<span class="_ _74"> </span>150</div><div class="t m0 x8d h3 ycb ff1 fs1 fc0 sc0 ls43 ws1">XC7K325T<span class="_ _76"> </span>8<span class="_ _6"> </span>250<span class="_ _74"> </span>150<span class="_ _6"> </span>8<span class="_ _73"> </span>250<span class="_ _77"> </span>150<span class="_ _78"> </span>16<span class="_ _78"> </span>350<span class="_ _74"> </span>150<span class="_ _78"> </span>16<span class="_ _78"> </span>350<span class="_ _50"> </span>150</div><div class="t m0 x8d h3 ycc ff1 fs1 fc0 sc0 ls43 ws1">XC7K355T<span class="_ _79"> </span>24<span class="_ _78"> </span>300<span class="_ _6"> </span>0</div><div class="t m0 x8d h3 ycd ff1 fs1 fc0 sc0 ls43 ws1">XC7K410T<span class="_ _76"> </span>8<span class="_ _6"> </span>250<span class="_ _74"> </span>150<span class="_ _6"> </span>8<span class="_ _73"> </span>250<span class="_ _77"> </span>150<span class="_ _78"> </span>16<span class="_ _78"> </span>350<span class="_ _74"> </span>150<span class="_ _78"> </span>16<span class="_ _78"> </span>350<span class="_ _50"> </span>150</div><div class="t m0 x8d h3 yce ff1 fs1 fc0 sc0 ls43 ws1">XC7K420T<span class="_ _79"> </span>28<span class="_ _78"> </span>380<span class="_ _6"> </span>0<span class="_ _4f"> </span>32<span class="_ _78"> </span>400<span class="_ _6"> </span>0</div><div class="t m0 x8d h3 ycf ff1 fs1 fc0 sc0 ls43 ws1">XC7K480T</div><div class="t m0 xb3 h3 yd0 ff1 fs1 fc0 sc0 ls43 ws1">28<span class="_ _78"> </span>380<span class="_ _6"> </span>0<span class="_ _4f"> </span>32<span class="_ _78"> </span>400<span class="_ _6"> </span>0</div><div class="t m0 x11 h3 yd1 ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 yd2 ff1 fs1 fc0 sc0 ls5 ws4">1.<span class="_ _28"> </span>All packages liste<span class="_ _4"></span>d are Pb-free. Some<span class="_ _4"></span> packages are a<span class="_ _1"></span>vailable in Pb option.</div><div class="t m0 x11 h3 yd3 ff1 fs1 fc0 sc0 ls61 ws4c">2.<span class="_ _28"> </span>Devices in<span class="_ _4"></span> FBG676 and FFG676 <span class="_ _4"></span>are f<span class="_ _1"></span>o<span class="_ _2"></span>otprint compatib<span class="_ _4"></span>le.</div><div class="t m0 x11 h3 yd4 ff1 fs1 fc0 sc0 ls61 ws4c">3.<span class="_ _28"> </span>Devices in<span class="_ _4"></span> FBG900 and FFG900 <span class="_ _4"></span>are f<span class="_ _1"></span>o<span class="_ _2"></span>otprint compatib<span class="_ _4"></span>le.</div><div class="t m0 x11 h3 yd5 ff1 fs1 fc0 sc0 ls3e ws41">4.<span class="_ _28"> </span>HR = High Range I/O with support for I/O v<span class="_ _1"></span>oltage from 1.2V to 3.3V<span class="_ _29"></span>.</div><div class="t m0 x11 h3 yd6 ff1 fs1 fc0 sc0 ls44 ws4d">5.<span class="_ _28"> </span>HP = High P<span class="_ _1"></span>erformance I/O with suppor<span class="_ _2"></span>t fo<span class="_ _1"></span>r <span class="_ _2"></span>I/O vo<span class="_ _4"></span>ltage from 1.2V to 1.8V<span class="_ _29"></span>.</div><div class="t m0 x1 h6 yd7 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 7<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls62 ws4e">Virtex-7 FPGA Feature Summary</span></div><div class="t m0 x97 h3 yd8 ff2 fs1 fc0 sc0 ls6 ws1">Device</div><div class="t m0 xb4 hb yd9 ff2 fs9 fc1 sc0 ls33 ws1">(1)</div><div class="t m0 xb5 h3 yda ff2 fs1 fc0 sc0 ls63 ws1">Logic </div><div class="t m0 xb6 h3 ydb ff2 fs1 fc0 sc0 ls64 ws1">Cells</div><div class="t m0 xb7 h3 ydc ff2 fs1 fc0 sc0 ls65 ws4f">Configurable Logic </div><div class="t m0 x2c h3 ydd ff2 fs1 fc0 sc0 ls55 ws44">Blocks (CLBs)</div><div class="t m0 xb8 h3 yda ff2 fs1 fc0 sc0 ls7 ws1">DSP </div><div class="t m0 xb9 h3 ydb ff2 fs1 fc0 sc0 ls32 ws1">Slices</div><div class="t m0 xba hb yde ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x82 h3 ydf ff2 fs1 fc0 sc0 ls2e ws50">Block RAM Bloc<span class="_ _1"></span>ks</div><div class="t m0 xbb hb ye0 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xa8 h3 yda ff2 fs1 fc0 sc0 ls31 ws1">CMTs</div><div class="t m0 x75 hb yde ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xbc h3 yda ff2 fs1 fc0 sc0 ls7 ws1">PCIe</div><div class="t m0 xbd hb yde ff2 fs9 fc1 sc0 ls35 ws1">(6)</div><div class="t m0 xbe h3 yd8 ff2 fs1 fc0 sc0 ls49 ws1">GTX<span class="_ _7a"> </span>GTH<span class="_ _7b"> </span>GTZ</div><div class="t m0 x12 h3 yda ff2 fs1 fc0 sc0 ls66 ws1">XADC </div><div class="t m0 x60 h3 ydb ff2 fs1 fc0 sc0 ls2c ws1">Blocks</div><div class="t m0 xbf h3 yda ff2 fs1 fc0 sc0 ls3c ws51">T<span class="_ _1"></span>otal I/O </div><div class="t m0 xbf h3 ydb ff2 fs1 fc0 sc0 ls3d ws1">Banks</div><div class="t m0 x6e hb yde ff2 fs9 fc1 sc0 ls35 ws1">(7)</div><div class="t m0 xc0 h3 ye1 ff2 fs1 fc0 sc0 ls67 ws1">Max </div><div class="t m0 xc1 h3 yd8 ff2 fs1 fc0 sc0 ls7 ws1">User </div><div class="t m0 xc1 h3 ye2 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x28 hb ye3 ff2 fs9 fc1 sc0 ls33 ws1">(8)</div><div class="t m0 x40 h3 yd8 ff2 fs1 fc0 sc0 ls41 ws1">SLRs</div><div class="t m0 xc2 hb yd9 ff2 fs9 fc1 sc0 ls35 ws1">(9)</div><div class="t m0 xc3 h3 ye4 ff2 fs1 fc0 sc0 ls3e ws1">Slices</div><div class="t m0 xc4 hb ye5 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 xc5 h3 ye6 ff2 fs1 fc0 sc0 ls7 ws1">Max </div><div class="t m0 x9b h3 ye4 ff2 fs1 fc0 sc0 ls42 ws1">Distributed </div><div class="t m0 xc6 h3 ye7 ff2 fs1 fc0 sc0 ls53 ws47">RAM (Kb)</div><div class="t m0 xc7 h3 ye4 ff2 fs1 fc0 sc0 ls2c ws1">18<span class="_"> </span>Kb<span class="_ _2c"> </span>36<span class="_"> </span>Kb</div><div class="t m0 xc8 h3 ye8 ff2 fs1 fc0 sc0 ls3f ws1">Max </div><div class="t m0 xc8 h3 ye9 ff2 fs1 fc0 sc0 ls42 ws1">(Kb)</div><div class="t m0 x8 h3 yea ff1 fs1 fc0 sc0 ls3e ws52">XC7V585T<span class="_ _3e"> </span>582,720<span class="_ _53"> </span>91,050<span class="_ _7c"> </span>6,938<span class="_ _5f"> </span>1,260 1,590<span class="_ _6"> </span>795 <span class="_ _7d"> </span>28,620<span class="_ _6"> </span>18<span class="_ _7c"> </span>3<span class="_ _64"> </span>36<span class="_ _7e"> </span>0<span class="_ _64"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>17<span class="_ _2e"> </span>850<span class="_ _3e"> </span>N/A</div><div class="t m0 x8 h3 yeb ff1 fs1 fc0 sc0 ls3e ws53">XC7V2000T<span class="_ _28"> </span>1,954,560<span class="_ _7f"> </span>305,400<span class="_ _7e"> </span>21,550<span class="_ _7c"> </span>2,160 2,584<span class="_ _80"> </span>1,292<span class="_ _53"> </span>46,<span class="_ _4"></span>512<span class="_ _6"> </span>24<span class="_ _7c"> </span>4<span class="_ _64"> </span>36<span class="_ _7e"> </span>0<span class="_ _64"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>24<span class="_ _3c"> </span>1,200<span class="_ _3c"> </span>4</div><div class="t m0 x8 h3 yec ff1 fs1 fc0 sc0 ls3e ws1">XC7VX330T<span class="_ _2d"> </span>326,400<span class="_ _53"> </span>51,000<span class="_ _7c"> </span>4,388<span class="_ _2e"> </span>1,1<span class="_ _4"></span>20<span class="_ _2d"> </span>1,500<span class="_ _6"> </span>750<span class="_ _7e"> </span>27,000<span class="_ _6"> </span>14<span class="_ _62"> </span>2<span class="_ _3c"> </span>0<span class="_ _7e"> </span>28<span class="_ _7e"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>14<span class="_ _2e"> </span>700<span class="_ _3e"> </span>N/A</div><div class="t m0 x8 h3 yed ff1 fs1 fc0 sc0 ls3e ws1">XC7VX415T<span class="_ _2d"> </span>412,160<span class="_ _53"> </span>64,400<span class="_ _7c"> </span>6,525<span class="_ _2e"> </span>2,1<span class="_ _4"></span>60<span class="_ _2d"> </span>1,760<span class="_ _6"> </span>880<span class="_ _7e"> </span>31,680<span class="_ _6"> </span>12<span class="_ _62"> </span>2<span class="_ _3c"> </span>0<span class="_ _7e"> </span>48<span class="_ _7e"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>12<span class="_ _2e"> </span>600<span class="_ _3e"> </span>N/A</div><div class="t m0 x8 h3 yee ff1 fs1 fc0 sc0 ls3e ws1">XC7VX485T<span class="_ _2d"> </span>485,760<span class="_ _53"> </span>75,900<span class="_ _7c"> </span>8,175<span class="_ _2e"> </span>2,8<span class="_ _4"></span>00<span class="_ _2d"> </span>2,060<span class="_ _80"> </span>1,030<span class="_ _81"> </span>37,080<span class="_ _6"> </span>14<span class="_ _7c"> </span>4<span class="_ _64"> </span>56<span class="_ _7e"> </span>0<span class="_ _64"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>14<span class="_ _2e"> </span>700<span class="_ _3e"> </span>N/A</div><div class="t m0 x8 h3 yef ff1 fs1 fc0 sc0 ls3e ws1">XC7VX550T<span class="_ _2d"> </span>554,240<span class="_ _53"> </span>86,600<span class="_ _7c"> </span>8,725<span class="_ _2e"> </span>2,8<span class="_ _4"></span>80<span class="_ _2d"> </span>2,360<span class="_ _80"> </span>1,180<span class="_ _81"> </span>42,480<span class="_ _6"> </span>20<span class="_ _7c"> </span>2<span class="_ _7c"> </span>0<span class="_ _7e"> </span>80<span class="_ _7e"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>16<span class="_ _2e"> </span>600<span class="_ _3e"> </span>N/A</div><div class="t m0 x8 h3 yf0 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX690T<span class="_ _2d"> </span>693,120<span class="_ _50"> </span>108,300<span class="_ _82"> </span>10,888<span class="_ _7c"> </span>3,600<span class="_ _2d"> </span>2,940<span class="_ _80"> </span>1,470<span class="_ _81"> </span>52,920<span class="_ _6"> </span>20<span class="_ _7c"> </span>3<span class="_ _7c"> </span>0<span class="_ _7e"> </span>80<span class="_ _7e"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>20<span class="_ _3c"> </span>1,000<span class="_ _7e"> </span>N/A</div><div class="t m0 x8 h3 yf1 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX980T<span class="_ _2d"> </span>979,200<span class="_ _50"> </span>153,000<span class="_ _82"> </span>13,838<span class="_ _7c"> </span>3,600<span class="_ _2d"> </span>3,000<span class="_ _80"> </span>1,500<span class="_ _81"> </span>54,000<span class="_ _6"> </span>18<span class="_ _7c"> </span>3<span class="_ _7c"> </span>0<span class="_ _7e"> </span>72<span class="_ _7e"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>18<span class="_ _2e"> </span>880<span class="_ _3e"> </span>N/A</div><div class="t m0 x8 h3 yf2 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX1140T<span class="_ _7b"> </span>1,139,200<span class="_ _7f"> </span>178,000<span class="_ _7e"> </span>17,700<span class="_ _7c"> </span>3,360<span class="_ _2d"> </span>3,760<span class="_ _80"> </span>1,880<span class="_ _81"> </span>67,680<span class="_ _6"> </span>24<span class="_ _7c"> </span>4<span class="_ _7c"> </span>0<span class="_ _7e"> </span>96<span class="_ _7e"> </span>0<span class="_ _2e"> </span>1<span class="_ _56"> </span>22<span class="_ _3c"> </span>1,100<span class="_ _3c"> </span>4</div><div class="t m0 x8 h3 yf3 ff1 fs1 fc0 sc0 ls3e ws1">XC7VH580T<span class="_ _2d"> </span>580,<span class="_ _4"></span>480<span class="_ _53"> </span>90,700<span class="_ _7c"> </span>8,850<span class="_ _5f"> </span>1,680<span class="_ _2d"> </span>1,880<span class="_ _6"> </span>940<span class="_ _7e"> </span>33,840<span class="_ _6"> </span>12<span class="_ _62"> </span>2<span class="_ _3c"> </span>0<span class="_ _7e"> </span>48<span class="_ _82"> </span>8<span class="_ _5f"> </span>1<span class="_ _2f"> </span>12<span class="_ _2e"> </span>600<span class="_ _40"> </span>2</div><div class="t m0 x8 h3 yf4 ff1 fs1 fc0 sc0 ls3e ws1">XC7VH870T<span class="_ _2d"> </span>876,<span class="_ _4"></span>160<span class="_ _50"> </span>136,900<span class="_ _7e"> </span>13,275<span class="_ _62"> </span>2,520<span class="_ _2d"> </span>2,<span class="_ _4"></span>820<span class="_ _80"> </span>1,410<span class="_ _81"> </span>50,760<span class="_ _6"> </span>18<span class="_ _7c"> </span>3<span class="_ _7c"> </span>0<span class="_ _7e"> </span>72<span class="_ _2d"> </span>16<span class="_ _7c"> </span>1<span class="_ _2f"> </span>13<span class="_ _2e"> </span>650<span class="_ _40"> </span>3</div><div class="t m0 x11 h3 yf5 ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 yf6 ff1 fs1 fc0 sc0 ls5 ws4">1.<span class="_ _28"> </span>EasyP<span class="_ _1"></span>ath™-7 FPGAs are also availab<span class="_ _1"></span>le to provide a fast,<span class="_ _4"></span> simple, and risk-free solution f<span class="_ _1"></span>or cost reducing Vir<span class="_ _2"></span>te<span class="_ _4"></span>x-7 T and Virte<span class="ls68 ws54">x-7 XT FPGA designs</span></div><div class="t m0 x11 h3 yf7 ff1 fs1 fc0 sc0 ls6 ws32">2.<span class="_ _28"> </span>Each 7<span class="_"> </span>series FPGA slice co<span class="_ _1"></span>ntains four LUTs and e<span class="_ _4"></span>ight flip-flops<span class="_ _1"></span><span class="ls3d ws33">; only some slices can use thei<span class="ls37 ws34">r LUTs as distrib<span class="_ _4"></span>uted RAM or SR<span class="ls3e ws1">Ls<span class="_ _4"></span>.</span></span></span></div><div class="t m0 x11 h3 yf8 ff1 fs1 fc0 sc0 ls3f ws35">3.<span class="_ _28"> </span>Each DSP slice contains a pre-adde<span class="_ _4"></span>r<span class="_ _1"></span>, a 25<span class="_"> </span>x<span class="_"> </span>18 multiplier<span class="_ _1"></span>, an adder, and<span class="_ _4"></span> an accumulator<span class="_ _1"></span>.</div><div class="t m0 x11 h3 yf9 ff1 fs1 fc0 sc0 ls44 ws35">4.<span class="_ _28"> </span>Block RAMs are<span class="_ _4"></span> fundamentally 36<span class="_"> </span>Kb in size; each b<span class="_ _1"></span>lock can also be used as two independe<span class="_ _4"></span>nt 18 Kb bloc<span class="_ _1"></span>ks.</div><div class="t m0 x11 h3 yfa ff1 fs1 fc0 sc0 ls44 ws35">5.<span class="_ _28"> </span>Each CMT contains one MMCM and one PLL.</div><div class="t m0 x11 h3 yfb ff1 fs1 fc0 sc0 ls37 ws55">6.<span class="_ _28"> </span>Virtex-7 T FPGA Interf<span class="_ _1"></span>ace Blocks f<span class="_ _1"></span>or PCI Express support up to x8<span class="ls7 ws56"> Gen <span class="_ _4"></span>2. Virtex-7 XT and Virtex-<span class="_ _4"></span>7 HT Interf<span class="_ _4"></span>ace Bloc<span class="_ _1"></span>ks for PCI<span class="ls4 ws57"> Express support up to x8 Gen 3, with the </span></span></div><div class="t m0 xc9 h3 yfc ff1 fs1 fc0 sc0 ls6 ws49">ex<span class="_ _4"></span>ception of the XC7VX485T de<span class="_ _1"></span>vice, which suppor<span class="_ _2"></span>ts x8 Gen 2.</div><div class="t m0 x11 h3 yfd ff1 fs1 fc0 sc0 ls6 ws32">7.<span class="_ _28"> </span>Does not include con<span class="_ _1"></span>f<span class="_ _2"></span>iguration<span class="_ _4"></span> Bank 0.</div><div class="t m0 x11 h3 yfe ff1 fs1 fc0 sc0 ls6 ws36">8.<span class="_ _28"> </span>This number does not include GTP<span class="_ _8"></span>, GTX, GTH, or GTZ transceiv<span class="_ _1"></span>ers.</div><div class="t m0 x11 h3 yff ff1 fs1 fc0 sc0 ls6 ws32">9.<span class="_ _28"> </span>Super logic regions <span class="_ _1"></span>(SLRs) are the constituent parts of FPGAs <span class="ls40 ws58">that u<span class="_ _4"></span>se SSI technology<span class="_ _29"></span>. Vir<span class="_ _2"></span>tex-7 HT d<span class="_ _4"></span>evices use S<span class="_ _4"></span>SI technology<span class="ls69 ws59"> to conn<span class="_ _1"></span>ect SLRs with 28.05 Gb/s </span></span></div><div class="t m0 xc9 h3 y100 ff1 fs1 fc0 sc0 ls3e ws1">transceiv<span class="_ _1"></span>ers.</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595080/bg5.jpg"><div class="t m0 x12 h6 y4e ff2 fs4 fc0 sc0 ls29 ws2a">7<span class="_"> </span>Series FPGA<span class="_ _1"></span>s Overview</div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">DS180 (v1.13) November 30, 2012<span class="_ _0"> </span><span class="fc1 ls1 ws1">www<span class="_ _1"></span>.xilinx.com</span></div><div class="t m0 x1 h2 y2 ff2 fs0 fc0 sc0 ls2 ws2">Adv<span class="_ _1"></span>a<span class="_ _2"></span>nce Product Specificatio<span class="_ _2"></span>n<span class="_ _3"> </span><span class="ff1 ls3 ws1">5</span></div><div class="t m0 x1 h6 y90 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 8<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls4c ws3d">Virtex-7 FPGA Dev<span class="_ _4"></span>ice-P<span class="_ _1"></span>ackage Combinatio<span class="_ _1"></span>ns and Maximum I/Os</span></div><div class="t m0 xca h3 y91 ff2 fs1 fc0 sc0 ls6a ws1">Packag<span class="_ _2"></span>e</div><div class="t m0 xcb hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 xcc h3 y91 ff2 fs1 fc0 sc0 ls41 ws1">FFG1157<span class="_ _c"> </span>FFG1761</div><div class="t m0 xcd hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x73 h3 y91 ff2 fs1 fc0 sc0 ls3e ws1">FHG1761</div><div class="t m0 xce hb y92 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x5a h3 y91 ff2 fs1 fc0 sc0 ls3e ws1">FLG1925</div><div class="t m0 xcf h3 y93 ff2 fs1 fc0 sc0 ls6b ws5a">Size (mm)<span class="_ _83"> </span>35 x 35<span class="_ _70"> </span>42.5 x 42.5<span class="_ _71"> </span>45 x 45<span class="_ _84"> </span>45 x 45</div><div class="t m0 xd0 h3 y94 ff2 fs1 fc0 sc0 ls6c ws5b">Ball Pitch<span class="_ _85"> </span>1.0<span class="_ _86"> </span>1.0<span class="_ _87"> </span>1.0<span class="_ _88"> </span>1.0</div><div class="t m0 xd1 h3 y95 ff2 fs1 fc0 sc0 ls6 ws1">Device</div><div class="t m0 xa hc y101 ff2 fsa fc0 sc0 ls6d ws1">GTX</div><div class="t m0 xd2 hc y102 ff2 fsa fc0 sc0 ls6e ws1">GTH</div><div class="t m0 xd3 h3 y103 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 xd4 hc y101 ff2 fsa fc0 sc0 ls3 ws1">GTX<span class="_ _7b"> </span>GTH</div><div class="t m0 xd5 h3 y103 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 xd6 hc y104 ff2 fsa fc0 sc0 ls3 ws1">GTX<span class="_ _89"> </span>GTH</div><div class="t m0 xd7 h3 y103 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x4f h3 y105 ff2 fs1 fc0 sc0 ls3c ws1">GTX</div><div class="t m0 x50 h3 y103 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 x6f h3 y106 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xa3 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 xd8 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x9b hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xd h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xba hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 xd9 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x82 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xc8 h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xce hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 xda h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x75 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xdb h3 y99 ff2 fs1 fc0 sc0 ls36 ws1">HR</div><div class="t m0 xdc hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x3d h3 y99 ff2 fs1 fc0 sc0 ls31 ws5c"> HP</div><div class="t m0 x52 hb y98 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 x8 h3 y9a ff1 fs1 fc0 sc0 ls4 ws1">XC7V585T<span class="_ _3d"> </span>20<span class="_ _6"> </span>0<span class="_ _3e"> </span>0<span class="_ _73"> </span>600<span class="_ _80"> </span>36<span class="_ _55"> </span>0<span class="_ _44"> </span>100<span class="_ _77"> </span>750</div><div class="t m0 x8 h3 y9b ff1 fs1 fc0 sc0 ls4 ws1">XC7V2000T<span class="_ _8a"> </span><span class="ls3e">36<span class="_ _73"> </span>0<span class="_ _69"> </span>0<span class="_ _7e"> </span>850<span class="_ _80"> </span>16<span class="_ _62"> </span>0<span class="_ _3f"> </span>1,200</span></div><div class="t m0 x8 h3 y107 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX330T<span class="_ _2d"> </span>0<span class="_ _6"> </span>20<span class="_ _3d"> </span>0<span class="_ _73"> </span>600<span class="_ _44"> </span>0<span class="_ _6"> </span>28<span class="_ _2d"> </span>50<span class="_ _8b"> </span>650</div><div class="t m0 x8 h3 y108 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX415T<span class="_ _8b"> </span>0<span class="_ _6"> </span>20<span class="_ _4f"> </span>0<span class="_ _73"> </span>600</div><div class="t m0 x8 h3 y109 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX485T<span class="_ _77"> </span>20<span class="_ _6"> </span>0<span class="_ _3e"> </span>0<span class="_ _73"> </span>600<span class="_ _80"> </span>28<span class="_ _55"> </span>0<span class="_ _69"> </span>0<span class="_ _7e"> </span>700</div><div class="t m0 x8 h3 y10a ff1 fs1 fc0 sc0 ls3e ws1">XC7VX550T</div><div class="t m0 x8 h3 y10b ff1 fs1 fc0 sc0 ls3e ws1">XC7VX690T<span class="_ _8b"> </span>0<span class="_ _6"> </span>20<span class="_ _4f"> </span>0<span class="_ _73"> </span>600<span class="_ _2d"> </span>0<span class="_ _6"> </span>36<span class="_ _82"> </span>0<span class="_ _7e"> </span>850</div><div class="t m0 x8 h3 y10c ff1 fs1 fc0 sc0 ls3e ws1">XC7VX980T</div><div class="t m0 x8 h3 y10d ff1 fs1 fc0 sc0 ls3e ws1">XC7VX1140T</div><div class="t m0 x11 h3 y10e ff2 fs1 fc0 sc0 ls41 ws1">Notes: </div><div class="t m0 x11 h3 y10f ff1 fs1 fc0 sc0 ls5 ws4">1.<span class="_ _28"> </span>All packages liste<span class="_ _4"></span>d are Pb-free. Some<span class="_ _4"></span> packages are a<span class="_ _1"></span>vailable in Pb option.</div><div class="t m0 x11 h3 y110 ff1 fs1 fc0 sc0 ls51 ws36">2.<span class="_ _28"> </span>Devices in FFG1761 and FHG17<span class="_ _4"></span>61 are foo<span class="_ _4"></span>tprint compatible<span class="_ _1"></span>.</div><div class="t m0 x11 h3 y111 ff1 fs1 fc0 sc0 ls3e ws41">3.<span class="_ _28"> </span>HR = High Range I/O with support for I/O v<span class="_ _1"></span>oltage from 1.2V to 3.3V<span class="_ _29"></span>.</div><div class="t m0 x11 h3 y112 ff1 fs1 fc0 sc0 ls44 ws4d">4.<span class="_ _28"> </span>HP = High P<span class="_ _1"></span>erformance I/O with suppor<span class="_ _2"></span>t fo<span class="_ _1"></span>r <span class="_ _2"></span>I/O vo<span class="_ _4"></span>ltage from 1.2V to 1.8V<span class="_ _29"></span>.</div><div class="t m0 x1 h6 y113 ff3 fs4 fc0 sc0 ls1f ws22">Ta<span class="_ _a"></span>b<span class="_ _a"></span>l<span class="_ _a"></span>e<span class="_ _a"></span> 9<span class="_ _a"></span>:<span class="_ _b"> </span><span class="ff2 ls4c ws3d">Virtex-7 FPGA Dev<span class="_ _4"></span>ice-P<span class="_ _1"></span>ackage Combinatio<span class="_ _1"></span>ns and Maximum I/Os -<span class="_ _4"></span> Continued</span></div><div class="t m0 xca h3 y114 ff2 fs1 fc0 sc0 ls6a ws1">Packag<span class="_ _2"></span>e</div><div class="t m0 xcb hb y115 ff2 fs9 fc1 sc0 ls35 ws1">(1)</div><div class="t m0 xdd h3 y114 ff2 fs1 fc0 sc0 ls41 ws1">FFG1158<span class="_ _2f"> </span>FFG1926</div><div class="t m0 x64 hb y115 ff2 fs9 fc1 sc0 ls33 ws1">(2)</div><div class="t m0 x47 h3 y114 ff2 fs1 fc0 sc0 ls2c ws1">FLG1926</div><div class="t m0 x72 hb y115 ff2 fs9 fc1 sc0 ls35 ws1">(2)</div><div class="t m0 x1b h3 y114 ff2 fs1 fc0 sc0 ls5 ws1">FFG1927<span class="_ _31"> </span>FFG1<span class="_ _4"></span>928</div><div class="t m0 xde hb y115 ff2 fs9 fc1 sc0 ls33 ws1">(3)</div><div class="t m0 xdf h3 y114 ff2 fs1 fc0 sc0 ls2c ws1">FLG1928</div><div class="t m0 x5f hb y115 ff2 fs9 fc1 sc0 ls35 ws1">(3)</div><div class="t m0 x96 h3 y114 ff2 fs1 fc0 sc0 ls41 ws1">FFG1930</div><div class="t m0 xe0 hb y115 ff2 fs9 fc1 sc0 ls35 ws1">(4)</div><div class="t m0 xe1 h3 y114 ff2 fs1 fc0 sc0 ls41 ws1">FLG1930</div><div class="t m0 xe2 hb y115 ff2 fs9 fc1 sc0 ls60 ws1">(4)</div><div class="t m0 xcf h3 y116 ff2 fs1 fc0 sc0 ls47 ws5d">Size (mm)<span class="_ _36"> </span>35 <span class="_ _4"></span>x 35<span class="_ _45"> </span>45 x 45<span class="_ _45"> </span>45 x 45<span class="_ _45"> </span>45 x 45<span class="_ _8c"> </span>45 x 45<span class="_ _45"> </span>45 x 45<span class="_ _6c"> </span>45 x 4<span class="_ _4"></span>5<span class="_ _48"> </span>45 x 45</div><div class="t m0 xd0 h3 y117 ff2 fs1 fc0 sc0 ls6f ws5e">Ball Pitch<span class="_ _6a"> </span>1.0<span class="_ _8d"> </span>1.0<span class="_ _8d"> </span>1.0<span class="_ _8e"> </span>1.0<span class="_ _8d"> </span>1.0<span class="_ _8e"> </span>1.0<span class="_ _5e"> </span>1.0<span class="_ _8f"> </span>1.0</div><div class="t m0 xd1 h3 y118 ff2 fs1 fc0 sc0 ls6 ws1">Device<span class="_ _7e"> </span>GTX<span class="_ _90"> </span>GTH</div><div class="t m0 x6f h3 y119 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x7f h3 y118 ff2 fs1 fc0 sc0 ls70 ws1">GTX<span class="_ _91"> </span>GTH</div><div class="t m0 xe3 h3 y119 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 xb9 h3 y118 ff2 fs1 fc0 sc0 ls4f ws1">GTX<span class="_ _90"> </span>G<span class="_ _2"></span>TH</div><div class="t m0 xe4 h3 y119 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 xe5 h3 y118 ff2 fs1 fc0 sc0 ls49 ws1">GTX<span class="_ _91"> </span>GTH</div><div class="t m0 xe h3 y119 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 xe6 h3 y118 ff2 fs1 fc0 sc0 ls49 ws1">GTX<span class="_ _90"> </span>GTH</div><div class="t m0 xe7 h3 y119 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 xbe h3 y118 ff2 fs1 fc0 sc0 ls49 ws1">GTX<span class="_ _91"> </span>GTH</div><div class="t m0 xe8 h3 y119 ff2 fs1 fc0 sc0 ls3c ws1">I/O</div><div class="t m0 xe9 h3 y118 ff2 fs1 fc0 sc0 ls4f ws1">GTX<span class="_ _b"> </span>GTH</div><div class="t m0 xea h3 y119 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 xeb h3 y118 ff2 fs1 fc0 sc0 ls4f ws1">GTX<span class="_ _b"> </span>GTH</div><div class="t m0 x59 h3 y119 ff2 fs1 fc0 sc0 ls49 ws1">I/O</div><div class="t m0 x6f h3 y11a ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x9a hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xe3 h3 y11c ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xec hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xe4 h3 y11c ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x82 hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xe h3 y11c ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xed hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xe7 h3 y11c ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xee hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xe8 h3 y11c ff2 fs1 fc0 sc0 ls31 ws1">HP</div><div class="t m0 xef hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xea h3 y11c ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 xf0 hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 x59 h3 y11c ff2 fs1 fc0 sc0 ls36 ws1">HP</div><div class="t m0 x2b hb y11b ff2 fs9 fc1 sc0 ls35 ws1">(5)</div><div class="t m0 xf1 h3 y11d ff1 fs1 fc0 sc0 ls3e ws1">XC7V585T</div><div class="t m0 xf1 h3 y11e ff1 fs1 fc0 sc0 ls3e ws1">XC7V2000T</div><div class="t m0 xf1 h3 y11f ff1 fs1 fc0 sc0 ls3e ws1">XC7VX330T</div><div class="t m0 xf1 h3 y120 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX415T<span class="_ _6"> </span>0<span class="_ _2d"> </span>48<span class="_ _92"> </span>350<span class="_ _93"> </span><span class="ls71">04<span class="_ _94"></span>8<span class="_ _95"></span>6<span class="_ _94"></span>0<span class="_ _94"></span>0</span></div><div class="t m0 xf1 h3 y121 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX485T<span class="_ _78"> </span>48<span class="_ _8b"> </span>0<span class="_ _28"> </span>350<span class="_ _96"> </span>56<span class="_ _2d"> </span>0<span class="_ _80"> </span>600<span class="_ _97"> </span><span class="ls46">24<span class="_ _55"> </span>0<span class="_ _44"> </span>700</span></div><div class="t m0 xf1 h3 y122 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX550T<span class="_ _6"> </span>0<span class="_ _2d"> </span>48<span class="_ _92"> </span>350<span class="_ _93"> </span><span class="ls71">08<span class="_ _94"></span>0<span class="_ _95"></span>6<span class="_ _94"></span>0<span class="_ _94"></span>0</span></div><div class="t m0 xf1 h3 y123 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX690T<span class="_ _6"> </span>0<span class="_ _2d"> </span>48<span class="_ _92"> </span>350<span class="_ _28"> </span>0<span class="_ _2d"> </span>64<span class="_ _98"> </span>720<span class="_ _99"> </span><span class="ls71">08<span class="_ _94"></span>0<span class="_ _95"></span>6<span class="_ _94"></span>0<span class="_ _94"></span>0<span class="_ _25"> </span><span class="ls3e">0<span class="_ _55"> </span>24<span class="_ _9a"> </span>1,000</span></span></div><div class="t m0 xf1 h3 y124 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX980T<span class="_ _9b"> </span><span class="ls71">06<span class="_ _94"></span>4<span class="_ _95"></span>7<span class="_ _94"></span>2<span class="_ _94"></span>0<span class="_ _25"> </span><span class="ls72">07<span class="_ _94"></span>2<span class="_ _95"></span>4<span class="_ _94"></span>8<span class="_ _9c"></span>0<span class="_ _4c"> </span><span class="ls73">02<span class="_ _9d"></span>4<span class="_ _9e"></span>9<span class="_ _9d"></span>0<span class="_ _9d"></span>0</span></span></span></div><div class="t m0 xf1 h3 y125 ff1 fs1 fc0 sc0 ls3e ws1">XC7VX1140T<span class="_ _9f"> </span><span class="ls72">06<span class="_ _94"></span>4<span class="_ _95"></span>7<span class="_ _9c"></span>2<span class="_ _94"></span>0<span class="_ _16"> </span><span class="ls3e">0<span class="_ _8b"> </span>96<span class="_ _98"> </span>480<span class="_ _a0"> </span>0<span class="_ _55"> </span>24<span class="_ _9a"> </span>1,100</span></span></div><div class="t m0 x1 h3 y126 ff2 fs1 fc0 sc0 ls2c ws1">Notes: </div><div class="t m0 x1 h3 y127 ff1 fs1 fc0 sc0 ls44 ws4d">1.<span class="_ _28"> </span>All packages listed<span class="_ _1"></span> <span class="_ _2"></span>are Pb-free.<span class="_ _4"></span> Some packa<span class="_ _4"></span>ges are av<span class="_ _1"></span>ailable in Pb option.</div><div class="t m0 x1 h3 y128 ff1 fs1 fc0 sc0 ls5 ws4">2.<span class="_ _28"> </span>Devices in FFG192<span class="_ _1"></span>6 <span class="_ _2"></span>and FLG1926 are f<span class="_ _1"></span>ootprint compatible.</div><div class="t m0 x1 h3 y129 ff1 fs1 fc0 sc0 ls5 ws4">3.<span class="_ _28"> </span>Devices in FFG192<span class="_ _1"></span>8 <span class="_ _2"></span>and FLG1928 are f<span class="_ _1"></span>ootprint compatible.</div><div class="t m0 x1 h3 y12a ff1 fs1 fc0 sc0 ls5 ws4">4.<span class="_ _28"> </span>Devices in FFG193<span class="_ _1"></span>0 <span class="_ _2"></span>and FLG1930 are f<span class="_ _1"></span>ootprint compatible.</div><div class="t m0 x1 h3 y12b ff1 fs1 fc0 sc0 ls44 ws4d">5.<span class="_ _28"> </span>HP = High P<span class="_ _1"></span>erformance I/O with support for I/O voltag<span class="_ _1"></span>e <span class="_ _2"></span>from 1.2V to 1.8V<span class="_ _29"></span>.</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>

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