ZIPMultiBoot 和 QuickBoot 参考资料 12.59MB

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MultiBoot 和 QuickBoot 参考资料.zip 大约有7个文件
  1. Fallback_test.zip 3.64MB
  2. ug470_7Series_Config.pdf 3.74MB
  3. xapp1081-quickboot-remote-update.pdf 1.35MB
  4. XAPP1081_QuickBoot.zip 5.36MB
  5. xapp1246-multiboot-bpi.pdf 1MB
  6. xapp1247-multiboot-spi.pdf 623.72KB
  7. xapp1247-multiboot-spi.zip 4.27MB

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MultiBoot 和 QuickBoot 参考资料
<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595069/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595069/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">7<span class="_"> </span>Series FPGAs</div><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls1 ws1">Configuration</div><div class="t m0 x1 h3 y3 ff2 fs1 fc0 sc0 ls2 ws2">User Guide</div><div class="t m0 x1 h4 y4 ff1 fs2 fc0 sc0 ls3 ws3">UG470 (v1.17) December<span class="_ _0"></span> 5, 2023</div><div class="t m0 x2 h5 y5 ff3 fs3 fc0 sc0 ls1 ws1">AMD Adaptive Computing is creating an environment where</div><div class="t m0 x2 h5 y6 ff3 fs3 fc0 sc0 ls1 ws1">employees, customers, and partners feel welcome and included.</div><div class="t m0 x2 h5 y7 ff3 fs3 fc0 sc0 ls1 ws1">To that end, we’re removing non-inclusive language from our</div><div class="t m0 x2 h5 y8 ff3 fs3 fc0 sc0 ls1 ws1">products and related collateral. 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Follow this</div><div class="t m0 x2 h5 ye ff3 fs3 fc1 sc0 ls1 ws1">link<span class="fc0"> for more information.</span></div><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595069/bg2.jpg"><div class="t m0 x3 h6 yf ff1 fs4 fc0 sc0 ls4 ws4">7<span class="_"> </span>Series FPGAs Configuration User Guide<span class="_ _1"> </span><span class="ff4 ls5 ws5">UG470 (v1.17) December 5, 2023</span></div></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595069/bg3.jpg"><div class="t m0 x3 h7 yf ff1 fs4 fc0 sc0 ls4 ws4">7<span class="_"> </span>Series FPGAs Configuration User Guide<span class="_ _2"> </span><span class="ls1 ws1">3</span></div><div class="t m0 x3 h6 y10 ff4 fs4 fc0 sc0 ls6 ws6">UG470 (v1.17) December 5, 2023</div><div class="t m0 x4 h8 y11 ff5 fs2 fc0 sc0 ls7 ws1"> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . .<span class="_ _3"> </span> 2</div><div class="t m0 x5 h9 y12 ff1 fs5 fc0 sc0 ls8 ws7">Preface: About This Guide</div><div class="t m0 x4 ha y13 ff6 fs6 fc0 sc0 ls9 ws8">Guide Contents<span class="_ _3"> </span><span class="ff5 fs2 ls7 ws1"> <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . .<span class="_ _3"> </span> <span class="ls1">5</span></span></div><div class="t m0 x4 h8 y14 ff5 fs2 fc0 sc0 ls7 ws1"> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . .<span class="_ _3"> </span> 5</div><div class="t m0 x5 h9 y15 ff1 fs5 fc0 sc0 lsa ws9">Chapter<span class="_"> </span>1: Configuration Overview</div><div class="t m0 x4 ha y16 ff6 fs6 fc0 sc0 lsb ws1">Overview<span class="ff5 fs2 ls7"> . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . .<span class="_ _3"> </span> 7</span></div><div class="t m0 x4 ha y17 ff6 fs6 fc0 sc0 lsc wsa">7 Series FPGAs Configuration Differences from Previous FPGA Generations<span class="_ _3"> </span><span class="ff5 fs2 ls7 ws1">. . . . . .<span class="_ _3"> </span> 8</span></div><div class="t m0 x4 ha y18 ff6 fs6 fc0 sc0 ls1 wsb">Design Considerations<span class="ff5 fs2 ls7 ws1"> . . . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . .<span class="_ _3"> </span> 9</span></div><div class="t m0 x4 ha y19 ff6 fs6 fc0 sc0 ls9 ws8">Configuration Factors<span class="_ _4"></span><span class="ff5 fs2 lsd wsc"> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . .<span class="_ _3"> </span> 14</span></div><div class="t m0 x4 ha y1a ff6 fs6 fc0 sc0 lse wsd">3D ICs Based on SSI Technology<span class="_ _5"></span><span class="ff5 fs2 lsd wsc"> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . .<span class="_ _3"> </span> 14</span></div><div class="t m0 x4 ha y1b ff6 fs6 fc0 sc0 lsf wse">Configuration Debugging<span class="_ _6"></span><span class="ff5 fs2 lsd wsc"> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 15</span></div><div class="t m0 x5 h9 y1c ff1 fs5 fc0 sc0 ls10 wsf">Chapter<span class="_"> </span>2: Configuration Interfaces</div><div class="t m0 x4 ha y1d ff6 fs6 fc0 sc0 ls11 ws10">Configuration Pins<span class="_ _4"></span><span class="ff5 fs2 lsd wsc"> . . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . .<span class="_ _3"> </span> 17</span></div><div class="t m0 x4 ha y1e ff6 fs6 fc0 sc0 ls12 ws11">Serial Configuration Mode<span class="_ _5"> </span><span class="ff5 fs2 lsd wsc">. . . . . . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 33</span></div><div class="t m0 x4 ha y1f ff6 fs6 fc0 sc0 ls13 ws12">SelectMAP Configuration Mode<span class="_ _7"> </span><span class="ff5 fs2 lsd wsc">. . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 36</span></div><div class="t m0 x4 ha y20 ff6 fs6 fc0 sc0 ls12 ws13">SelectMAP ABORT<span class="_ _5"></span><span class="ff5 fs2 lsd wsc"> . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . .<span class="_ _3"> </span> 43</span></div><div class="t m0 x4 ha y21 ff6 fs6 fc0 sc0 ls14 ws14">Master SPI Configuration Mode<span class="_ _6"></span><span class="ff5 fs2 lsd wsc">. . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . .<span class="_ _3"> </span> 46</span></div><div class="t m0 x4 ha y22 ff6 fs6 fc0 sc0 ls1 wsb">Master BPI Configuration Interface<span class="_ _5"></span><span class="ff5 fs2 lsd wsc"> . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . .<span class="_ _3"> </span> 54</span></div><div class="t m0 x4 ha y23 ff6 fs6 fc0 sc0 ls15 ws15">JTAG Interface<span class="_ _6"></span><span class="ff5 fs2 lsd wsc"> . . . . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 62</span></div><div class="t m0 x5 h9 y24 ff1 fs5 fc0 sc0 ls10 wsf">Chapter<span class="_"> </span>3: Boundary-Scan <span class="ls16 ws16">and JTAG Configuration</span></div><div class="t m0 x4 ha y25 ff6 fs6 fc0 sc0 lsc ws1">Introduction<span class="_ _4"></span><span class="ff5 fs2 ls7"> . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . <span class="ls17 ws17">. .<span class="_ _3"> </span> 63</span></span></div><div class="t m0 x4 ha y26 ff6 fs6 fc0 sc0 ls18 ws18">Boundary-Scan for 7<span class="_"> </span>Series Devi<span class="ls9 ws8">ces Using IEEE Standard 1149.1<span class="_ _3"> </span><span class="ff5 fs2 ls19 ws19">. . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . .<span class="_ _3"> </span> 63</span></span></div><div class="t m0 x4 ha y27 ff6 fs6 fc0 sc0 ls1a ws1a">Boundary-Scan Design Considerations<span class="_ _5"> </span><span class="ff5 fs2 lsd wsc">. . . . . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 66</span></div><div class="t m0 x5 h9 y28 ff1 fs5 fc0 sc0 ls1b ws1b">Chapter<span class="_"> </span>4: Dynamic Reconfiguration Po<span class="_ _6"></span>rt (DRP)</div><div class="t m0 x4 ha y29 ff6 fs6 fc0 sc0 ls14 ws14">Dynamic Reconfiguration of Functional Blocks<span class="_ _3"> </span><span class="ff5 fs2 lsd wsc">. . . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 69</span></div><div class="t m0 x5 h9 y2a ff1 fs5 fc0 sc0 ls8 ws1c">Chapter<span class="_"> </span>5: Configuration Details</div><div class="t m0 x4 ha y2b ff6 fs6 fc0 sc0 lsf wse">Configuration Data File Formats<span class="_ _6"></span><span class="ff5 fs2 lsd wsc"> . . . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 73</span></div><div class="t m0 x4 ha y2c ff6 fs6 fc0 sc0 ls11 ws10">Generating Memory Files<span class="_ _3"> </span><span class="ff5 fs2 lsd wsc">. . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . .<span class="_ _3"> </span> 75</span></div><div class="t m0 x4 ha y2d ff6 fs6 fc0 sc0 lse wsd">Configuration Sequence<span class="_ _3"> </span><span class="ff5 fs2 lsd wsc"> . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . .<span class="_ _3"> </span> 78</span></div><div class="t m0 x4 ha y2e ff6 fs6 fc0 sc0 ls1c ws1d">Bitstream Security<span class="_ _3"> </span><span class="ff5 fs2 lsd wsc"> . . . . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . .<span class="_ _3"> </span> 89</span></div><div class="t m0 x4 ha y2f ff6 fs6 fc0 sc0 ls1d ws1">eFUSE<span class="_ _3"> </span><span class="ff5 fs2 ls7"> . . . . . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . <span class="ls1e ws1e">. .<span class="_ _0"></span> . . . . .<span class="_ _3"> </span> 94</span></span></div><div class="t m0 x4 ha y30 ff6 fs6 fc0 sc0 ls1f ws1f">Bitstream Composition<span class="_ _7"> </span><span class="ff5 fs2 lsd wsc"> . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . .<span class="_ _3"> </span> 96</span></div><div class="t m0 x3 hb y31 ff7 fs7 fc0 sc0 ls20 ws20">T<span class="_ _8"></span>able of Contents</div><div class="c x6 y32 w2 hc"><div class="t m2 x7 hd y33 ff8 fs8 fc2 sc0 ls1 ws1"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595069/bg4.jpg"><div class="t m0 x3 h7 yf ff1 fs4 fc0 sc0 ls1 ws1">4<span class="_ _2"> </span><span class="ls21 ws21">7<span class="_"> </span>Series FPGAs C<span class="_ _6"></span>onfiguration <span class="_ _6"></span>User Guide</span></div><div class="t m0 x8 h6 y10 ff4 fs4 fc0 sc0 ls5 ws5">UG470 (v1.17) December 5, 2023</div><div class="t m0 x4 ha y34 ff6 fs6 fc0 sc0 ls9 ws8">Configuration Memory Frames<span class="ff5 fs2 ls7 ws1">. . . . . . . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . .<span class="_ _3"> </span> 100</span></div><div class="t m0 x4 ha y35 ff6 fs6 fc0 sc0 ls1a ws1a">Configuration Packets<span class="ff5 fs2 ls7 ws1"> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 100</span></div><div class="t m0 x4 ha y36 ff6 fs6 fc0 sc0 lsf wse">Configuration Registers<span class="ff5 fs2 ls7 ws1">. . . . . . . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 101</span></div><div class="t m0 x4 ha y37 ff6 fs6 fc0 sc0 ls22 ws22">Device Identifier and Device DNA<span class="_ _5"> </span><span class="ff5 fs2 ls7 ws1"> . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 114</span></div><div class="t m0 x5 h9 y38 ff1 fs5 fc0 sc0 ls16 ws16">Chapter<span class="_"> </span>6: Readback and <span class="ls10 wsf">Configuration Verification</span></div><div class="t m0 x4 ha y39 ff6 fs6 fc0 sc0 ls23 ws23">Preparing a Design for Readback<span class="_ _4"></span><span class="ff5 fs2 ls7 ws1">. . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 119</span></div><div class="t m0 x4 ha y3a ff6 fs6 fc0 sc0 ls24 ws24">Readback Comm<span class="ws25">and Sequences<span class="ff5 fs2 ls7 ws1"> . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . .<span class="_ _3"> </span> 120</span></span></div><div class="t m0 x4 ha y3b ff6 fs6 fc0 sc0 ls12 ws13">Verifying Readback Data<span class="_ _4"></span><span class="ff5 fs2 ls7 ws1"> . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 129</span></div><div class="t m0 x4 ha y3c ff6 fs6 fc0 sc0 ls14 ws26">Readback Capture<span class="_ _7"> </span><span class="ff5 fs2 ls7 ws1"> . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _3"> </span> 132</span></div><div class="t m0 x5 h9 y3d ff1 fs5 fc0 sc0 ls16 ws16">Chapter<span class="_"> </span>7: Reconfigur<span class="ls10 wsf">ation and MultiBoot</span></div><div class="t m0 x4 ha y3e ff6 fs6 fc0 sc0 ls13 ws27">Fallback MultiBoot<span class="_ _4"></span><span class="ff5 fs2 ls7 ws1">. . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 133</span></div><div class="t m0 x4 ha y3f ff6 fs6 fc0 sc0 ls1 wsb">IPROG Reconfiguration<span class="_ _6"></span><span class="ff5 fs2 ls7 ws1"> . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . .<span class="_ _3"> </span> 137</span></div><div class="t m0 x4 ha y40 ff6 fs6 fc0 sc0 ls12 ws11">Status Register for <span class="_ _0"></span>Fallback and IPROG Reconfiguration<span class="_ _6"></span><span class="ff5 fs2 ls7 ws1"> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . .<span class="_ _3"> </span> 139</span></div><div class="t m0 x4 ha y41 ff6 fs6 fc0 sc0 ls9 ws1">Watchdog<span class="_ _3"> </span><span class="ff5 fs2 ls7"> . . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . .<span class="_ _3"> </span> 140</span></div><div class="t m0 x4 ha y42 ff6 fs6 fc0 sc0 ls25 ws28">Design Examples<span class="_ _6"></span><span class="ff5 fs2 ls7 ws1"> . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> .<span class="_"> </span> <span class="_ _0"></span>142</span></div><div class="t m0 x5 h9 y43 ff1 fs5 fc0 sc0 ls10 wsf">Chapter<span class="_"> </span>8: Readback CRC</div><div class="t m0 x4 ha y44 ff6 fs6 fc0 sc0 lsc wsa">SEU Detection<span class="_ _9"> </span><span class="ff5 fs2 ls26 ws29"> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> .<span class="_ _3"> </span> 14<span class="ls1 ws1">3</span></span></div><div class="t m0 x4 ha y45 ff6 fs6 fc0 sc0 ls1 wsb">SEU Correction<span class="ff5 fs2 ls7 ws1"> . . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . .<span class="_ _3"> </span> 145</span></div><div class="t m0 x5 h9 y46 ff1 fs5 fc0 sc0 lsa ws9">Chapter<span class="_"> </span>9: Multiple <span class="ws2a">FPGA Configuration</span></div><div class="t m0 x4 ha y47 ff6 fs6 fc0 sc0 ls1a ws1a">Serial Daisy Chain Configuration<span class="_ _6"></span><span class="ff5 fs2 ls7 ws1">. . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 147</span></div><div class="t m0 x4 ha y48 ff6 fs6 fc0 sc0 ls18 ws2b">Ganged Serial Configuration<span class="_ _9"> </span><span class="ff5 fs2 ls7 ws1">. . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 149</span></div><div class="t m0 x4 ha y49 ff6 fs6 fc0 sc0 ls11 ws10">Multiple Device SelectMAP Configuration<span class="_ _7"> </span><span class="ff5 fs2 ls7 ws1"> . . . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . .<span class="_ _3"> </span> 151</span></div><div class="t m0 x4 ha y4a ff6 fs6 fc0 sc0 ls1a ws1a">Parallel Daisy Chain Configuration<span class="_ _5"> </span><span class="ff5 fs2 ls7 ws1">. . . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . .<span class="_ _3"> </span> 152</span></div><div class="t m0 x4 ha y4b ff6 fs6 fc0 sc0 ls1a ws2c">Ganged SelectMAP Configuration<span class="_ _7"> </span><span class="ff5 fs2 ls7 ws1">. . . . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> .<span class="_ _3"> </span> 153</span></div><div class="t m0 x5 h9 y4c ff1 fs5 fc0 sc0 lsa ws2d">Chapter<span class="_"> </span>10: Advanced JTAG Usage</div><div class="t m0 x4 ha y4d ff6 fs6 fc0 sc0 lsc ws1">Introduction<span class="_ _4"></span><span class="ff5 fs2 ls7"> . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . <span class="ls27 ws2e">. 1<span class="_ _8"></span>5<span class="_ _a"></span>5</span></span></div><div class="t m0 x4 ha y4e ff6 fs6 fc0 sc0 ls1a ws2c">JTAG Configur<span class="ls13 ws1">ation/Readback<span class="_ _7"> </span><span class="ff5 fs2 ls7"> . . . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _3"> </span> 155</span></span></div><div class="t m0 x5 h9 y4f ff1 fs5 fc0 sc0 ls10 wsf">Appendix<span class="_"> </span>A: Additional Resources and Legal Notices</div><div class="t m0 x4 ha y50 ff6 fs6 fc0 sc0 ls1a ws1a">Finding Additional Documentation<span class="_ _4"></span><span class="ff5 fs2 ls7 ws1"> . . . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> .<span class="_ _3"> </span> 169</span></div><div class="t m0 x4 ha y51 ff6 fs6 fc0 sc0 ls18 ws18">Support Resources<span class="_ _7"> </span><span class="ff5 fs2 ls7 ws1"> . . . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> .<span class="_ _3"> </span> 169</span></div><div class="t m0 x4 ha y52 ff6 fs6 fc0 sc0 ls28 ws1">References<span class="_ _9"> </span><span class="ff5 fs2 ls7">. . . . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . .<span class="ls29 ws2f"> . .<span class="_ _3"> </span> 169</span></span></div><div class="t m0 x4 ha y53 ff6 fs6 fc0 sc0 ls1f ws30">Revision History<span class="_ _3"> </span><span class="ff5 fs2 ls7 ws1"> . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _3"> </span> 170</span></div><div class="t m0 x4 ha y54 ff6 fs6 fc0 sc0 lsc wsa">Please Read: Important Legal Notices<span class="_ _6"></span><span class="ff5 fs2 ls7 ws1">. . . . . .<span class="_ _0"></span> . . . . . <span class="_ _0"></span>. . . . . . . <span class="_ _0"></span>. . . . . . <span class="_ _0"></span>. . . . . .<span class="_ _0"></span> . . . . . . .<span class="_ _0"></span> . . . .<span class="_ _3"> </span> 173</span></div><div class="c x9 y32 w2 hc"><div class="t m2 x7 hd y33 ff8 fs8 fc2 sc0 ls1 ws1"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89595069/bg5.jpg"><div class="t m0 x3 h7 yf ff1 fs4 fc0 sc0 ls4 ws4">7<span class="_"> </span>Series FPGAs Configuration User Guide<span class="_ _2"> </span><span class="ls1 ws1">5</span></div><div class="t m0 x3 h6 y10 ff4 fs4 fc0 sc0 ls6 ws6">UG470 (v1.17) December 5, 2023</div><div class="t m0 xa he y55 ff9 fs9 fc0 sc0 ls2a ws1">Pr<span class="_ _b"></span>eface</div><div class="t m0 x3 hb y56 ff7 fs7 fc0 sc0 ls2b ws31">About This Guide</div><div class="t m0 xb h8 y57 ff5 fs2 fc0 sc0 ls2c ws32">AMD 7 series FPGAs include four <span class="ls2d ws33">FPGA<span class="_ _0"></span> families<span class="_ _0"></span> that are all design<span class="ls2e ws34">ed for lowest power to enable </span></span></div><div class="t m0 xb h8 y58 ff5 fs2 fc0 sc0 ls2f ws35">a common design to scale across <span class="ls30 ws36">families for optimal power, <span class="_ _0"></span>pe<span class="ls31 ws37">rformance, and cost. The <span class="_ _c"></span>AMD </span></span></div><div class="t m0 xb h8 y59 ff5 fs2 fc0 sc0 ls30 ws38">Spartan&#8482;-7 family i<span class="_ _6"></span>s the lowest density <span class="_ _6"></span>with the lowest cost entry <span class="_ _6"></span>point into the 7 series portfolio. </div><div class="t m0 xb h8 y5a ff5 fs2 fc0 sc0 ls32 ws39">The <span class="_ _c"></span>AMD <span class="_ _c"></span>A<span class="_ _6"></span>rtix&#8482;-7 family is optimized for highest p<span class="_ _6"></span>erformance-per-watt and bandwidth-per-watt </div><div class="t m0 xb h8 y5b ff5 fs2 fc0 sc0 ls33 ws3a">for cost-sensitive, high-vol<span class="_ _6"></span>ume applications. The <span class="_ _c"></span>AMD Kintex&#8482;-7 fam<span class="_ _6"></span>ily is an innovative class of </div><div class="t m0 xb h8 y5c ff5 fs2 fc0 sc0 ls30 ws36">FPGAs optimized for the best pr<span class="ls34 ws3b">ice-performance. The AMD V<span class="_ _b"></span>irtex<span class="ls32 ws3c">&#8482;-7 family is optim<span class="_ _6"></span>ized for </span></span></div><div class="t m0 xb h8 y5d ff5 fs2 fc0 sc0 ls2d ws3d">highest system performance and capacity<span class="_ _b"></span>. This guide<span class="ls34 ws3e"> serves as a technical reference describing the </span></div><div class="t m0 xb h8 y5e ff5 fs2 fc0 sc0 ls31 ws3f">7 series FPGAs configuration. </div><div class="t m0 xb h8 y5f ff5 fs2 fc0 sc0 ls31 ws1">This <span class="ff9 ls35 ws40">7 Series FPGAs Configuration<span class="_ _6"></span> User Guide</span><span class="ls32 ws3c"> is part of an overall set of document<span class="_ _6"></span>ation on the 7 </span></div><div class="t m0 xb h8 y60 ff5 fs2 fc0 sc0 ls2f ws35">series FPGAs, which is avai<span class="ls36 ws41">lable on the <span class="_ _c"></span>AMD website at <span class="fc1 ls37 ws1">www<span class="_ _c"></span>.xilinx<span class="_ _6"></span>.com/</span></span></div><div class="t m0 xc h8 y61 ff5 fs2 fc1 sc0 ls2d ws1">documentation<span class="fc0 ls1">.</span></div><div class="t m0 x3 hf y62 ff1 fsa fc0 sc0 ls38 ws42">Guide Contents</div><div class="t m0 xb h8 y63 ff5 fs2 fc0 sc0 ls34 ws43">This manual contains these topics:</div><div class="t m0 xb h8 y64 ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls39 ws44">Chapter<span class="_"> </span>1, Configuration <span class="_ _6"></span>Overview</span></div><div class="t m0 xb h8 y65 ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls34 ws3e">Chapter<span class="_"> </span>2, Configuration Interfaces</span></div><div class="t m0 xb h8 y66 ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls33 ws45">Chapter<span class="_"> </span>3, Boundary-Scan an<span class="_ _6"></span>d JT<span class="_ _b"></span>AG Configuration</span></div><div class="t m0 xb h8 y67 ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls3a ws46">Chapter<span class="_"> </span>4, Dynamic Reconfiguration Port (DRP)</span></div><div class="t m0 xb h8 y68 ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls3a ws3">Chapter<span class="_"> </span>5, Configuration <span class="_ _6"></span>Details</span></div><div class="t m0 xb h8 y69 ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls3b ws47">Chapter<span class="_"> </span>6, Readback and Co<span class="ls3c ws48">nfiguration V<span class="_ _b"></span>erification</span></span></div><div class="t m0 xb h8 y6a ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls3a ws46">Chapter<span class="_"> </span>7, Reconfiguration and MultiBoot</span></div><div class="t m0 xb h8 y6b ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls2d ws3d">Chapter<span class="_"> </span>8, Readback CRC</span></div><div class="t m0 xb h8 y6c ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls3c ws49">Chapter<span class="_"> </span>9, Multiple <span class="_ _6"></span>FPGA<span class="_ _c"></span> Configuration</span></div><div class="t m0 xb h8 y6d ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls34 ws43">Chapter<span class="_"> </span>10, <span class="_ _c"></span>Advanced JT<span class="_ _b"></span>AG Usage</span></div><div class="t m0 xb h8 y6e ff5 fs2 fc0 sc0 ls1 ws1">&#8226;<span class="_ _d"> </span><span class="fc1 ls32 ws4a">Appendix<span class="_"> </span>A, <span class="_ _0"></span>Additional Resources and <span class="_ _6"></span>Legal Notices</span></div><div class="c x6 y32 w2 hc"><div class="t m2 x7 hd y33 ff8 fs8 fc2 sc0 ls1 ws1"><span class="fc3 sc0">S</span><span class="fc3 sc0">e</span><span class="fc3 sc0">n</span><span class="fc3 sc0">d</span><span class="fc3 sc0"> </span><span class="fc3 sc0">F</span><span class="fc3 sc0">e</span><span class="fc3 sc0">e</span><span class="fc3 sc0">d</span><span class="fc3 sc0">b</span><span class="fc3 sc0">a</span><span class="fc3 sc0">c</span><span class="fc3 sc0">k</span></div></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.568627,0.000000,0.000000,1.568627,0.000000,0.000000]}'></div></div>
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