MultiBoot 和 QuickBoot 参考资料
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MultiBoot 和 QuickBoot 参考资料
7 Series FPGAs
Configuration
User Guide
UG470 (v1.17) December 5, 2023
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7 Series FPGAs Configuration User Guide UG470 (v1.17) December 5, 2023
7 Series FPGAs Configuration User Guide 3
UG470 (v1.17) December 5, 2023
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Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Chapter 1: Configuration Overview
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Series FPGAs Configuration Differences from Previous FPGA Generations . . . . . . 8
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Configuration Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3D ICs Based on SSI Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Configuration Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 2: Configuration Interfaces
Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SelectMAP Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SelectMAP ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Master SPI Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Master BPI Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 3: Boundary-Scan and JTAG Configuration
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Boundary-Scan for 7 Series Devices Using IEEE Standard 1149.1 . . . . . . . . . . . . . . . . 63
Boundary-Scan Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 4: Dynamic Reconfiguration Port (DRP)
Dynamic Reconfiguration of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Chapter 5: Configuration Details
Configuration Data File Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Generating Memory Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Bitstream Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
eFUSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Bitstream Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table of Contents
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4 7 Series FPGAs Configuration User Guide
UG470 (v1.17) December 5, 2023
Configuration Memory Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Configuration Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Device Identifier and Device DNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Chapter 6: Readback and Configuration Verification
Preparing a Design for Readback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Readback Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Verifying Readback Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Readback Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Chapter 7: Reconfiguration and MultiBoot
Fallback MultiBoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
IPROG Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Status Register for Fallback and IPROG Reconfiguration . . . . . . . . . . . . . . . . . . . . . . 139
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Chapter 8: Readback CRC
SEU Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SEU Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 9: Multiple FPGA Configuration
Serial Daisy Chain Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Ganged Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Multiple Device SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Parallel Daisy Chain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Ganged SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Chapter 10: Advanced JTAG Usage
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
JTAG Configuration/Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Appendix A: Additional Resources and Legal Notices
Finding Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Please Read: Important Legal Notices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
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7 Series FPGAs Configuration User Guide 5
UG470 (v1.17) December 5, 2023
Preface
About This Guide
AMD 7 series FPGAs include four FPGA families that are all designed for lowest power to enable
a common design to scale across families for optimal power, performance, and cost. The AMD
Spartan™-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio.
The AMD Artix™-7 family is optimized for highest performance-per-watt and bandwidth-per-watt
for cost-sensitive, high-volume applications. The AMD Kintex™-7 family is an innovative class of
FPGAs optimized for the best price-performance. The AMD Virtex™-7 family is optimized for
highest system performance and capacity. This guide serves as a technical reference describing the
7 series FPGAs configuration.
This 7 Series FPGAs Configuration User Guide is part of an overall set of documentation on the 7
series FPGAs, which is available on the AMD website at www.xilinx.com/
documentation.
Guide Contents
This manual contains these topics:
• Chapter 1, Configuration Overview
• Chapter 2, Configuration Interfaces
• Chapter 3, Boundary-Scan and JTAG Configuration
• Chapter 4, Dynamic Reconfiguration Port (DRP)
• Chapter 5, Configuration Details
• Chapter 6, Readback and Configuration Verification
• Chapter 7, Reconfiguration and MultiBoot
• Chapter 8, Readback CRC
• Chapter 9, Multiple FPGA Configuration
• Chapter 10, Advanced JTAG Usage
• Appendix A, Additional Resources and Legal Notices
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