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JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
JESD79-3A
September 2007
JEDEC
STANDARD
DDR3 SDRAM Specification
(Revision of JESD79-3)
NOTICE
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The information included in JEDEC standards and publications represents a sound approach to
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Published by
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Organizations may obtain permission to reproduce a limited number of copies
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or call (703) 907-7559
JEDEC Standard No. 79-3A
Contents
i
1 Scope..........................................................................................................................................1
2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
2.1 DDR3 SDRAM x4 Ballout using MO-207 (Top view: see balls through package) ...... 3
2.2 DDR3 SDRAM x8 Ballout using MO-207 (Top view: see balls through package) ..... 4
2.3 DDR3 SDRAM x16 Ballout using MO-207 (Top view: see balls through package)..... 5
2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207 (Top view: see balls through
package).............................................................................................. 6
2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207 (Top view: see balls through
package).............................................................................................. 7
2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207 (Top view: see balls through
package).............................................................................................. 8
2.7 Pinout Description..............................................................................................................9
2.8 DDR3 SDRAM Addressing.............................................................................................11
2.8.1 512Mb .....................................................................................................................11
2.8.2 1Gb ...........................................................................................................................11
2.8.3 2Gb ..........................................................................................................................11
2.8.4 4Gb ..........................................................................................................................11
2.8.5 8Gb ..........................................................................................................................12
3 Functional Description.............................................................................................................13
3.1 Simplified State Diagram.................................................................................................13
3.2 Basic Functionality...........................................................................................................14
3.3 RESET and Initialization Procedure ................................................................................15
3.3.1 Power-up Initialization Sequence.............................................................................15
3.3.2 Reset Initialization with Stable Power .....................................................................17
3.4 Register Definition ...........................................................................................................18
3.4.1 Programming the Mode Registers............................................................................18
3.4.2 Mode Register MR0 .................................................................................................18
3.4.3 Mode Register MR1 .................................................................................................22
3.4.4 Mode Register MR2 .................................................................................................25
3.4.5 Mode Register MR3 .................................................................................................27
4 DDR3 SDRAM Command Description and Operation...........................................................29
4.1 Command Truth Table .....................................................................................................29
4.2 CKE Truth Table..............................................................................................................31
4.3 No OPeration (NOP) Command ......................................................................................32
4.4 Deselect Command ..........................................................................................................32
4.5 DLL-off Mode..................................................................................................................33
4.6 DLL on/off switching procedure......................................................................................34
4.6.1 DLL “on” to DLL “off” Procedure ..........................................................................34
4.6.2 DLL “off” to DLL “on” Procedure ..........................................................................35
4.7 Input clock frequency change ..........................................................................................36
4.8 Write Leveling .................................................................................................................38
4.8.1 DRAM setting for write leveling & DRAM termination function in that mode......38
4.8.2 Procedure Description ..............................................................................................39
4.8.3 Write Leveling Mode Exit........................................................................................41
4.9 Extended Temperature Usage ..........................................................................................42
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