STMS003F3的TIM1和TIM2定时器，ADC采样与普通IO输入输出配置（新手必看，保姆级） 9.69MB

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STMS003F3的TIM1和TIM2定时器，ADC采样与普通IO输入输出配置（新手必看，保姆级）

<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89634253/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89634253/bg1.jpg"/><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls0 ws0">October 2017<span class="_ _0"> </span>DocID14587 Rev 1<span class="_ _1"></span>4<span class="_ _2"> </span>1/467</div><div class="t m0 x2 h3 y2 ff1 fs1 fc1 sc0 ls1 ws1">1</div><div class="t m0 x3 h4 y3 ff2 fs2 fc0 sc0 ls2 ws1">RM0016</div><div class="t m0 x4 h4 y4 ff2 fs2 fc0 sc0 ls3 ws2">Reference manual</div><div class="t m0 x5 h5 y5 ff1 fs3 fc0 sc0 ls4 ws3">STM8S Series and STM8AF Series 8-bit microcontrollers<span class="_ _3"></span><span class="ls1 ws1"> </span></div><div class="t m0 x6 h6 y6 ff2 fs4 fc0 sc0 ls5 ws1">Introduction</div><div class="t m0 x6 h7 y7 ff1 fs5 fc0 sc0 ls6 ws4">This reference manual provides complete information fo<span class="_ _4"></span>r application developers on how to </div><div class="t m0 x6 h7 y8 ff1 fs5 fc0 sc0 ls7 ws5">use STM8S Series and STM8AF Series mi<span class="_ _4"></span>crocontroller memor<span class="_ _4"></span>y and peripherals. </div><div class="t m0 x6 h7 y9 ff1 fs5 fc0 sc0 ls8 ws6">The STM8AF Series<span class="_ _1"></span> of microcontrollers<span class="_ _1"></span> is designed for auto<span class="_ _1"></span>motive applicat<span class="_ _1"></span>ions, with </div><div class="t m0 x6 h7 ya ff1 fs5 fc0 sc0 ls9 ws7">diff<span class="_ _4"></span>erent memory densities, package<span class="_ _4"></span>s and peripherals:</div><div class="t m0 x6 h7 yb ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lsa ws8">The low-density STM8AF devices are the <span class="ls9 ws9">STM8<span class="_ _4"></span>AF6223/26 with 8 Kbytes of<span class="_ _4"></span> Flash </span></span></div><div class="t m0 x7 h7 yc ff1 fs5 fc0 sc0 lsb ws1">memory.</div><div class="t m0 x6 h7 yd ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lsc wsa">The medium-den<span class="_ _1"></span>sity STM8AF device<span class="_ _1"></span>s are the STM8AF62<span class="_ _1"></span>4x and STM8AF<span class="_ _1"></span>6266/68 </span></div><div class="t m0 x7 h7 ye ff1 fs5 fc0 sc0 lsd wsb">microcontrollers with 16 to <span class="_ _4"></span><span class="lse wsc">32 Kbytes of Flash memory. </span></div><div class="t m0 x6 h7 yf ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lsf wsd">The high-density STM8AF devices ar<span class="_ _4"></span>e the STM8AF52xx and STM8AF6269<span class="_ _4"></span>/8x/Ax </span></div><div class="t m0 x7 h7 y10 ff1 fs5 fc0 sc0 lsd wsb">microcontrollers with 32 to <span class="_ _4"></span>128 Kbytes of Flash memory. </div><div class="t m0 x6 h7 y11 ff1 fs5 fc0 sc0 lsd wse">The STM8S Series of microcontrollers is de<span class="ls10 wsf">signed for g<span class="_ _4"></span>eneral purpose applica<span class="_ _4"></span>tions, with </span></div><div class="t m0 x6 h7 y12 ff1 fs5 fc0 sc0 ls9 ws7">diff<span class="_ _4"></span>erent memory densities, package<span class="_ _4"></span>s and peripherals.</div><div class="t m0 x6 h7 y13 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 ls11 ws10">The value-line low-de<span class="_ _1"></span>nsity STM8S devices ar<span class="_ _1"></span>e the STM8S001<span class="_ _1"></span>xx/STM8S003<span class="_ _1"></span>xx </span></div><div class="t m0 x7 h7 y14 ff1 fs5 fc0 sc0 lsd wsb">microcontrollers with 8 Kbytes of Fla<span class="_ _4"></span>sh memory.</div><div class="t m0 x6 h7 y15 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 ls9 ws7">The value-line medi<span class="_ _4"></span>um-density STM8S devices are the STM8<span class="_ _4"></span>S005xx microcontrollers </span></div><div class="t m0 x7 h7 y16 ff1 fs5 fc0 sc0 ls12 ws11">with 32 Kbytes of Flash memory.</div><div class="t m0 x6 h7 y17 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 ls10 ws12">The value-line high-d<span class="_ _4"></span>ensity STM8S devices ar<span class="ls12 ws13">e the STM8S007xx micr<span class="_ _4"></span>ocontrollers with<span class="_ _4"></span> </span></span></div><div class="t m0 x7 h7 y18 ff1 fs5 fc0 sc0 lse wsc">64 Kbytes of Flash memory. </div><div class="t m0 x6 h7 y19 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 ls13 ws14">The access-line low-de<span class="_ _4"></span>nsity STM8S devices are the STM8S103xx a<span class="_ _4"></span>nd STM8S903xx </span></div><div class="t m0 x7 h7 y1a ff1 fs5 fc0 sc0 ls14 ws15">microcontrollers with 8 Kbytes of Fla<span class="_ _4"></span>sh memory. </div><div class="t m0 x6 h7 y1b ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lse ws16">The access-line m<span class="_ _4"></span>edium-density STM8S <span class="_ _4"></span>devic<span class="lsf wsd">es are the STM8S105<span class="_ _4"></span>xx microcontrollers </span></span></div><div class="t m0 x7 h7 y1c ff1 fs5 fc0 sc0 ls15 ws17">with 16 to 32 Kbytes of Flash memory. </div><div class="t m0 x6 h7 y1d ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lse wsc">The performance-lin<span class="_ _4"></span>e high-density STM8S devices are the STM8S207xx and </span></div><div class="t m0 x7 h7 y1e ff1 fs5 fc0 sc0 ls16 ws1">STM8S208xx m<span class="_ _1"></span>icrocontr<span class="_ _1"></span>ollers with 32<span class="_ _1"></span> to 128 Kb<span class="_ _1"></span>ytes of Flas<span class="_ _1"></span>h memory<span class="_ _1"></span>. </div><div class="t m0 x6 h7 y1f ff1 fs5 fc0 sc0 ls17 ws18">Refer to the product datasheet for orde<span class="_ _4"></span>ring information, pin description, mechanical an<span class="_ _4"></span>d </div><div class="t m0 x6 h7 y20 ff1 fs5 fc0 sc0 ls10 ws12">electrical device characteristics, an<span class="_ _4"></span>d for <span class="ls18 ws19">the complete list of <span class="ls12 ws13">available periphe<span class="_ _4"></span>rals.</span></span></div><div class="t m0 x6 h8 y21 ff2 fs6 fc0 sc0 ls19 ws1">Reference documents</div><div class="t m0 x6 h7 y22 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lse wsc">For information on progra<span class="_ _4"></span>mming, erasing and pr<span class="ls10 ws12">otection of the inter<span class="_ _4"></span>nal Flash memory </span></span></div><div class="t m0 x7 h7 y23 ff1 fs5 fc0 sc0 ls1a ws1a">please refer<span class="_ _1"></span> to the STM<span class="_ _1"></span>8S Series a<span class="_ _1"></span>nd STM8AF Ser<span class="_ _1"></span>ies Flas<span class="_ _1"></span>h progr<span class="_ _1"></span>amming ma<span class="_ _1"></span>nual </div><div class="t m0 x7 h7 y24 ff1 fs5 fc0 sc0 ls13 ws14">(PM0051), and to th<span class="_ _4"></span>e STM8 SWIM communication protocol and debu<span class="_ _4"></span>g module user </div><div class="t m0 x7 h7 y25 ff1 fs5 fc0 sc0 ls1b ws1b">manual (UM0470)<span class="_ _4"></span>.</div><div class="t m0 x6 h7 y26 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 lse wsc">For information on the STM8 core, r<span class="_ _4"></span>efer to STM8 CPU programming manual (PM0044).</span></div><div class="t m0 x6 h7 y27 ff3 fs5 fc0 sc0 ls1 ws1">•<span class="_ _5"> </span><span class="ff1 ls9 ws7">The bootloader user manua<span class="_ _4"></span>l (UM0560) descr<span class="ls12 ws11">ibes the usage of the integrated<span class="_ _4"></span> ROM </span></span></div><div class="t m0 x7 h7 y28 ff1 fs5 fc0 sc0 lsf ws1">bootloader.</div><div class="t m0 x8 h9 y2 ff4 fs1 fc2 sc0 ls1c ws1">www<span class="_ _4"></span>.st.com</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89634253/bg2.jpg"><div class="t m0 x1 ha y29 ff2 fs5 fc0 sc0 lsf ws1">Contents<span class="_ _6"> </span><span class="ls1d">RM0016</span></div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls1e ws1c">2/467<span class="_ _2"> </span>DocID1<span class="_ _1"></span>4587 Rev 14</div><div class="t m0 x1 hb y2a ff2 fs7 fc0 sc0 ls1f ws1">Contents</div><div class="t m0 x1 hc y2b ff2 fs8 fc0 sc0 ls20 ws1d">1<span class="_ _7"> </span>Central processing unit (CPU) <span class="_ _8"> </span>. <span class="ls21 ws1e">. . . . . . . . . . . . . . . . <span class="ls22 ws1f">. . . . . . . . . . . . . . . <span class="_ _9"></span>23</span></span></div><div class="t m0 x6 hd y2c ff1 fs6 fc0 sc0 ls23 ws20">1.1<span class="_ _a"> </span>CPU introduction <span class="_ _b"> </span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>23</div><div class="t m0 x6 hd y2d ff1 fs6 fc0 sc0 ls19 ws1">1.2<span class="_ _a"> </span>CPU registers <span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>23</div><div class="t m0 x9 h7 y2e ff1 fs5 fc0 sc0 ls1 ws21">1.2.1<span class="_ _a"> </span>Description of CPU <span class="_ _1"></span>registers <span class="_"> </span>. . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 23</div><div class="t m0 x9 h7 y2f ff1 fs5 fc0 sc0 ls24 ws21">1.2.2<span class="_ _a"> </span>STM8 CPU regis<span class="_ _1"></span>ter map <span class="_ _1"></span> . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 27</div><div class="t m0 x6 hd y30 ff1 fs6 fc0 sc0 ls23 ws20">1.3<span class="_ _a"> </span>Global configuration register (CFG_GCR) <span class="_ _8"> </span>. . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>27</div><div class="t m0 x9 h7 y31 ff1 fs5 fc0 sc0 ls25 ws22">1.3.1<span class="_ _a"> </span>Activation level <span class="_ _9"></span>. . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 27</div><div class="t m0 x9 h7 y32 ff1 fs5 fc0 sc0 ls25 ws22">1.3.2<span class="_ _a"> </span>SWIM dis<span class="_ _1"></span>able <span class="_ _1"></span>. . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 27</div><div class="t m0 x9 h7 y33 ff1 fs5 fc0 sc0 ls26 ws23">1.3.3<span class="_ _a"> </span>Description of global configuration register (CFG_GC<span class="_ _1"></span>R) <span class="_ _d"></span>. . . . . . . .<span class="_ _1"></span> . . . . 28</div><div class="t m0 x9 h7 y34 ff1 fs5 fc0 sc0 ls15 ws24">1.3.4<span class="_ _a"> </span>Global configuration register<span class="_ _4"></span> map and re<span class="ls1 ws21">set values <span class="_"> </span> . . . . . . . . . . . . . . <span class="_ _1"></span>. 28</span></div><div class="t m0 x1 hc y35 ff2 fs8 fc0 sc0 ls27 ws25">2<span class="_ _7"> </span>Boot ROM <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . <span class="ws1f">. . . . . . . . . . . . <span class="ls22 ws26">. . . . . . . . . . . <span class="_ _9"></span>29</span></span></div><div class="t m0 x1 hc y36 ff2 fs8 fc0 sc0 ls28 ws27">3<span class="_ _7"> </span>Memory and register map . . . . <span class="ls29 ws28">. . . . . . . . . . . . . . . . . <span class="ls22 ws1f">. . . . . . . . . . . . . . . <span class="_ _9"></span>30</span></span></div><div class="t m0 x6 hd y37 ff1 fs6 fc0 sc0 ls19 ws1">3.1<span class="_ _a"> </span>Memory layout <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>30</div><div class="t m0 x9 h7 y38 ff1 fs5 fc0 sc0 ls25 ws22">3.1.1<span class="_ _a"> </span>Memory map <span class="_ _9"></span> . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . 30</div><div class="t m0 x9 h7 y39 ff1 fs5 fc0 sc0 ls24 ws29">3.1.2<span class="_ _a"> </span>Stack handling <span class="_ _8"> </span>. . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . .<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 31</div><div class="t m0 x6 hd y3a ff1 fs6 fc0 sc0 ls23 ws20">3.2<span class="_ _a"> </span>Register description abbreviations <span class="_ _b"> </span>. . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>33</div><div class="t m0 x1 hc y3b ff2 fs8 fc0 sc0 ls2a ws2a">4<span class="_ _7"> </span>Flash prog<span class="_ _1"></span>ram memory and data EEP<span class="_ _1"></span>ROM <span class="_ _e"> </span> . <span class="ls2b ws2b">. . . . . . . . . . . <span class="ls2c ws2c">. . . . . . . . . <span class="_ _9"></span>34</span></span></div><div class="t m0 x6 hd y3c ff1 fs6 fc0 sc0 ls23 ws20">4.1<span class="_ _a"> </span>Flash and EEPROM introduction <span class="_ _8"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>34</div><div class="t m0 x6 hd y3d ff1 fs6 fc0 sc0 ls23 ws20">4.2<span class="_ _a"> </span>Flash and EEPROM glossary . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>34</div><div class="t m0 x6 hd y3e ff1 fs6 fc0 sc0 ls19 ws1">4.3<span class="_ _a"> </span>Main Flash memory features <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _c"> </span>35</div><div class="t m0 x6 hd y3f ff1 fs6 fc0 sc0 ls19 ws1">4.4<span class="_ _a"> </span>Memory organization <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>36</div><div class="t m0 x9 h7 y40 ff1 fs5 fc0 sc0 lse wsc">4.4.1<span class="_ _a"> </span>STM8S and STM8AF memory organization <span class="_ _f"> </span> <span class="ls2d ws2d">. . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _1"></span>36</span></div><div class="t m0 x9 h7 y41 ff1 fs5 fc0 sc0 ls18 ws2e">4.4.2<span class="_ _a"> </span>Memory access/<span class="_ _1"></span> wait state configuration <span class="_ _9"></span>. . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 40</div><div class="t m0 x9 h7 y42 ff1 fs5 fc0 sc0 ls2e ws2f">4.4.3<span class="_ _a"> </span>User boot area (UBC) <span class="_ _e"> </span> . . . . . . <span class="_ _1"></span>. . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 40</div><div class="t m0 x9 h7 y43 ff1 fs5 fc0 sc0 ls2f ws30">4.4.4<span class="_ _a"> </span>Data EEPROM (DA<span class="_ _10"></span>T<span class="_ _10"></span>A) <span class="_ _e"> </span> . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . . <span class="_ _1"></span>. . . 43</div><div class="t m0 x9 h7 y44 ff1 fs5 fc0 sc0 ls30 ws31">4.4.5<span class="_ _a"> </span>Main program area <span class="_"> </span> . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 43</div><div class="t m0 x9 h7 y45 ff1 fs5 fc0 sc0 ls25 ws22">4.4.6<span class="_ _a"> </span>Option bytes <span class="_ _d"></span>. . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 43</div><div class="t m0 x6 hd y46 ff1 fs6 fc0 sc0 ls19 ws1">4.5<span class="_ _a"> </span>Memory protection . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>44</div><div class="t m0 x9 h7 y47 ff1 fs5 fc0 sc0 ls1 ws21">4.5.1<span class="_ _a"> </span>Readout protection <span class="_"> </span> . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 44</div><div class="t m0 x9 h7 y48 ff1 fs5 fc0 sc0 ls31 ws32">4.5.2<span class="_ _a"> </span>Memory access security sys<span class="ls32 ws33">tem (MASS) <span class="_ _8"> </span> . . . . . . . . . . . . <span class="_ _1"></span>. . . . . . . . . . <span class="_ _1"></span>. 44</span></div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89634253/bg3.jpg"><div class="t m0 xa h2 y1 ff1 fs0 fc0 sc0 ls33 ws34">DocID14587 Rev 14<span class="_ _2"> </span>3/467</div><div class="t m0 x1 ha y29 ff2 fs5 fc0 sc0 ls1d ws1">RM0016<span class="_ _6"> </span><span class="ls14">Contents</span></div><div class="t m0 x2 h3 y2 ff1 fs1 fc1 sc0 ls34 ws1">16</div><div class="t m0 x9 h7 y49 ff1 fs5 fc0 sc0 ls30 ws31">4.5.3<span class="_ _a"> </span>Enabling write acc<span class="_ _1"></span>ess to option bytes <span class="_ _d"></span> . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . 45</div><div class="t m0 x6 hd y4a ff1 fs6 fc0 sc0 ls19 ws1">4.6<span class="_ _a"> </span>Memory programming <span class="_ _e"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>46</div><div class="t m0 x9 h7 y4b ff1 fs5 fc0 sc0 ls24 ws29">4.6.1<span class="_ _a"> </span>Read-while-write (RWW) <span class="_ _c"> </span>. . . . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 46</div><div class="t m0 x9 h7 y4c ff1 fs5 fc0 sc0 ls24 ws29">4.6.2<span class="_ _a"> </span>Byte programming <span class="_"> </span>. . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . 46</div><div class="t m0 x9 h7 y4d ff1 fs5 fc0 sc0 ls30 ws31">4.6.3<span class="_ _a"> </span>Word programming <span class="_ _e"> </span> . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . 47</div><div class="t m0 x9 h7 y4e ff1 fs5 fc0 sc0 ls18 ws2e">4.6.4<span class="_ _a"> </span>Block programming <span class="_ _9"></span> . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . <span class="ls2d ws2d">. .<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 47</span></div><div class="t m0 x9 h7 y4f ff1 fs5 fc0 sc0 ls30 ws31">4.6.5<span class="_ _a"> </span>Option byte programming <span class="_ _8"> </span> . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 49</div><div class="t m0 x6 hd y50 ff1 fs6 fc0 sc0 ls35 ws35">4.7<span class="_ _a"> </span>ICP (in-circuit programmin<span class="_ _4"></span>g) and IAP<span class="_ _4"></span> (in-application programming) <span class="_ _9"></span> . . . . <span class="_ _c"> </span>49</div><div class="t m0 x6 hd y51 ff1 fs6 fc0 sc0 ls19 ws1">4.8<span class="_ _a"> </span>Flash registers <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>51</div><div class="t m0 x9 h7 y52 ff1 fs5 fc0 sc0 ls30 ws31">4.8.1<span class="_ _a"> </span>Flash control register <span class="_ _1"></span>1 (FLASH_CR1) <span class="_ _e"> </span> . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>51</div><div class="t m0 x9 h7 y53 ff1 fs5 fc0 sc0 ls30 ws31">4.8.2<span class="_ _a"> </span>Flash control register <span class="_ _1"></span>2 (FLASH_CR2) <span class="_ _e"> </span> . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>52</div><div class="t m0 x9 h7 y54 ff1 fs5 fc0 sc0 ls6 ws36">4.8.3<span class="_ _a"> </span>Flash complementary control register<span class="_ _4"></span><span class="ls36 ws37"> 2 (FLASH_NCR2) <span class="_ _9"></span> <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 53</span></div><div class="t m0 x9 h7 y55 ff1 fs5 fc0 sc0 ls16 ws1">4.8.4<span class="_ _a"> </span>Flas<span class="_ _1"></span>h protec<span class="_ _1"></span>tion register<span class="_ _1"></span> (FLASH_FPR) <span class="_ _e"> </span> .<span class="_ _1"></span> <span class="ls2d ws2d">. . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 54</span></div><div class="t m0 x9 h7 y56 ff1 fs5 fc0 sc0 ls2e ws2f">4.8.5<span class="_ _a"> </span>Flash prot<span class="_ _1"></span>ection register (FLASH_NFPR) <span class="_"> </span>. . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 54</div><div class="t m0 x9 h7 y57 ff1 fs5 fc0 sc0 ls17 ws18">4.8.6<span class="_ _a"> </span>Flash program memory unprotecting key registe<span class="_ _4"></span>r (FLASH_PUKR) <span class="_ _8"> </span> . . . 54</div><div class="t m0 x9 h7 y58 ff1 fs5 fc0 sc0 ls17 ws18">4.8.7<span class="_ _a"> </span>Data EEPROM unpro<span class="ls37 ws38">tection key register (FLASH_DUKR) <span class="_ _e"> </span>. . . . . . . <span class="_ _1"></span>. . . 55</span></div><div class="t m0 x9 h7 y59 ff1 fs5 fc0 sc0 ls36 ws37">4.8.8<span class="_ _a"> </span>Flash status regist<span class="_ _1"></span>er (FLASH_IAPSR) <span class="_ _d"></span>. . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 55</div><div class="t m0 x9 h7 y5a ff1 fs5 fc0 sc0 ls17 ws39">4.8.9<span class="_ _a"> </span>Flash register map a<span class="_ _4"></span>nd reset values . . . <span class="ls2d ws2d">. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 56</span></div><div class="t m0 x1 hc y5b ff2 fs8 fc0 sc0 ls38 ws3a">5<span class="_ _7"> </span>Single wire interface module (SWIM)<span class="ls20 ws26"> and debug module (DM) <span class="_ _11"> </span> . . . . . <span class="_ _9"></span>57</span></div><div class="t m0 x6 hd y5c ff1 fs6 fc0 sc0 ls39 ws3b">5.1<span class="_ _a"> </span>SWIM and DM introduction <span class="_ _8"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>57</div><div class="t m0 x6 hd y5d ff1 fs6 fc0 sc0 ls39 ws3b">5.2<span class="_ _a"> </span>SWIM main features <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>57</div><div class="t m0 x6 hd y5e ff1 fs6 fc0 sc0 ls19 ws1">5.3<span class="_ _a"> </span>SWIM modes <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>57</div><div class="t m0 x1 hc y5f ff2 fs8 fc0 sc0 ls22 ws3c">6<span class="_ _7"> </span>Interrupt controller (ITC) <span class="_ _d"></span>. . . <span class="ls3a ws3d">. . . . . . . . . . . . <span class="ls27 ws25">. . . . . . . . . . . . <span class="ls20 ws2c">. . . . . . . . . . <span class="_ _9"></span>59</span></span></span></div><div class="t m0 x6 hd y60 ff1 fs6 fc0 sc0 ls19 ws1">6.1<span class="_ _a"> </span>ITC introduction <span class="_ _9"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>59</div><div class="t m0 x6 hd y61 ff1 fs6 fc0 sc0 ls19 ws1">6.2<span class="_ _a"> </span>Interrupt masking and processing flow <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>59</div><div class="t m0 x9 h7 y62 ff1 fs5 fc0 sc0 lsd wse">6.2.1<span class="_ _a"> </span>Servicing pending interrupts <span class="_ _b"> </span><span class="lsc ws3e"> . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 60</span></div><div class="t m0 x9 h7 y63 ff1 fs5 fc0 sc0 ls24 ws29">6.2.2<span class="_ _a"> </span>Interrupt sources <span class="_ _9"></span> . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _1"></span>61</div><div class="t m0 x6 hd y64 ff1 fs6 fc0 sc0 ls39 ws3b">6.3<span class="_ _a"> </span>Interrupts and low power modes <span class="_ _f"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>63</div><div class="t m0 x6 hd y65 ff1 fs6 fc0 sc0 ls39 ws3b">6.4<span class="_ _a"> </span>Activation level/low power mode<span class="_ _4"></span> control <span class="_ _c"> </span> . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>63</div><div class="t m0 x6 hd y66 ff1 fs6 fc0 sc0 ls39 ws3b">6.5<span class="_ _a"> </span>Concurrent and nested interrupt <span class="_ _4"></span>management . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _c"> </span>64</div><div class="t m0 x9 h7 y67 ff1 fs5 fc0 sc0 ls10 ws12">6.5.1<span class="_ _a"> </span>Concurrent interrupt management mode <span class="_ _d"></span>. . <span class="_ _1"></span><span class="ls2d ws2d">. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 64</span></div><div class="t m0 x9 h7 y68 ff1 fs5 fc0 sc0 ls10 ws12">6.5.2<span class="_ _a"> </span>Nested interrupt management mode <span class="_ _e"> </span>. . . . . <span class="_ _1"></span><span class="ls2d ws2d">. . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 65</span></div><div class="t m0 x6 hd y69 ff1 fs6 fc0 sc0 ls19 ws1">6.6<span class="_ _a"> </span>External interrupts <span class="_ _e"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>66</div><div class="t m0 x6 hd y6a ff1 fs6 fc0 sc0 ls23 ws20">6.7<span class="_ _a"> </span>Interrupt instructions <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>66</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89634253/bg4.jpg"><div class="t m0 x1 ha y29 ff2 fs5 fc0 sc0 lsf ws1">Contents<span class="_ _6"> </span><span class="ls1d">RM0016</span></div><div class="t m0 x1 h2 y1 ff1 fs0 fc0 sc0 ls1e ws1c">4/467<span class="_ _2"> </span>DocID1<span class="_ _1"></span>4587 Rev 14</div><div class="t m0 x6 hd y6b ff1 fs6 fc0 sc0 ls39 ws3b">6.8<span class="_ _a"> </span>Interrupt mapping <span class="_ _e"> </span>. . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>67</div><div class="t m0 x6 hd y6c ff1 fs6 fc0 sc0 ls19 ws1">6.9<span class="_ _a"> </span>ITC and EXTI registers <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>68</div><div class="t m0 x9 h7 y6d ff1 fs5 fc0 sc0 lsd wse">6.9.1<span class="_ _a"> </span>CPU condition code register interrupt bi<span class="ls11 ws3f">ts (CCR) <span class="_ _e"> </span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 68</span></div><div class="t m0 x9 h7 y6e ff1 fs5 fc0 sc0 ls3b ws40">6.9.2<span class="_ _a"> </span>So<span class="_ _1"></span>ftware prior<span class="_ _1"></span>ity register x (ITC<span class="_ _1"></span>_SPRx) <span class="_ _1"></span>. <span class="ls2d ws2d">.<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 69</span></div><div class="t m0 x9 h7 y6f ff1 fs5 fc0 sc0 ls3c ws41">6.9.3<span class="_ _a"> </span>Ext<span class="_ _1"></span>ernal interrup<span class="_ _1"></span>t control registe<span class="_ _1"></span>r 1 (<span class="ls18 ws2e">EXTI_CR1) <span class="_ _e"> </span>. . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 70</span></div><div class="t m0 x9 h7 y70 ff1 fs5 fc0 sc0 ls3c ws41">6.9.4<span class="_ _a"> </span>Ext<span class="_ _1"></span>ernal interrup<span class="_ _1"></span>t control registe<span class="_ _1"></span>r 1 (<span class="ls18 ws2e">EXTI_CR2) <span class="_ _e"> </span>. . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 71</span></div><div class="t m0 x9 h7 y71 ff1 fs5 fc0 sc0 lsa ws8">6.9.5<span class="_ _a"> </span>ITC and EXTI register map and reset values<span class="ls2d ws2d"> <span class="_ _1"></span>. . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . 72</span></div><div class="t m0 x1 hc y72 ff2 fs8 fc0 sc0 ls29 ws42">7<span class="_ _7"> </span>Power supply <span class="_ _f"></span>. . . . . . . . . . . <span class="ls27 ws25">. . . . . . . . . . . . <span class="ws1f">. . . . . . . . . . . . <span class="ls22 ws26">. . . . . . . . . . . <span class="_ _9"></span>73</span></span></span></div><div class="t m0 x1 hc y73 ff2 fs8 fc0 sc0 ls3d ws28">8<span class="_ _7"> </span>Reset (RST) <span class="_ _f"></span> . . . . . . . . . . . . <span class="ls27 ws25">. . . . . . . . . . . . <span class="ws1f">. . . . . . . . . . . . <span class="_ _4"></span><span class="ls22 ws26">. . . . . . . . . . . <span class="_ _9"></span>74</span></span></span></div><div class="t m0 x6 hd y74 ff1 fs6 fc0 sc0 ls19 ws1">8.1<span class="_ _a"> </span>“Reset state” and “under reset” definitions <span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>74</div><div class="t m0 x6 hd y75 ff1 fs6 fc0 sc0 ls23 ws20">8.2<span class="_ _a"> </span>Reset circuit description <span class="_ _e"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>74</div><div class="t m0 x6 hd y76 ff1 fs6 fc0 sc0 ls19 ws1">8.3<span class="_ _a"> </span>Internal reset sources <span class="_ _1"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>75</div><div class="t m0 x9 h7 y77 ff1 fs5 fc0 sc0 ls3e ws43">8.3.1<span class="_ _a"> </span>Power-on reset (POR) and br<span class="_ _4"></span>own-out rese<span class="ls1 ws21">t (BOR) <span class="_ _f"> </span>. . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . 75</span></div><div class="t m0 x9 h7 y78 ff1 fs5 fc0 sc0 ls24 ws21">8.3.2<span class="_ _a"> </span>Watchdog reset <span class="_ _d"></span> . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 75</div><div class="t m0 x9 h7 y79 ff1 fs5 fc0 sc0 ls11 ws3f">8.3.3<span class="_ _a"> </span>Software reset <span class="_ _d"></span> . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 76</div><div class="t m0 x9 h7 y7a ff1 fs5 fc0 sc0 ls11 ws3f">8.3.4<span class="_ _a"> </span>SWIM reset <span class="_ _e"> </span> . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>76</div><div class="t m0 x9 h7 y7b ff1 fs5 fc0 sc0 ls30 ws31">8.3.5<span class="_ _a"> </span>Illegal opcode reset <span class="_ _d"></span> . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . 76</div><div class="t m0 x9 h7 y7c ff1 fs5 fc0 sc0 ls11 ws3f">8.3.6<span class="_ _a"> </span>EMC reset <span class="_ _9"></span> . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>76</div><div class="t m0 x6 hd y7d ff1 fs6 fc0 sc0 ls23 ws20">8.4<span class="_ _a"> </span>RST register description <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>77</div><div class="t m0 x9 h7 y7e ff1 fs5 fc0 sc0 ls2e ws2f">8.4.1<span class="_ _a"> </span>Reset status register (RST_SR<span class="_ _1"></span>) <span class="_ _b"> </span> <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 77</div><div class="t m0 x6 hd y7f ff1 fs6 fc0 sc0 ls23 ws20">8.5<span class="_ _a"> </span>RST register map <span class="_ _e"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>77</div><div class="t m0 x1 hc y80 ff2 fs8 fc0 sc0 ls20 ws44">9<span class="_ _7"> </span>Clock control (CLK) . . . . . . . . <span class="ls29 ws28">. . . . . . . . . . . . . . . . . <span class="ls3f ws45">. . . . . . . . . . . . . . . . <span class="_ _9"></span>78</span></span></div><div class="t m0 x6 hd y81 ff1 fs6 fc0 sc0 ls19 ws1">9.1<span class="_ _a"> </span>Master clock sources . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>80</div><div class="t m0 x9 h7 y82 ff1 fs5 fc0 sc0 ls8 ws46">9.1.1<span class="_ _a"> </span>HSE<span class="_ _1"></span> (high-spee<span class="_ _1"></span>d external)<span class="_ _1"></span> clock signal <span class="_ _9"></span>. .<span class="_ _1"></span> <span class="ls2d ws2d">. . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 80</span></div><div class="t m0 x9 h7 y83 ff1 fs5 fc0 sc0 ls40 ws47">9.1.2<span class="_ _a"> </span>HSI (high-speed internal) clock signal <span class="_ _8"> </span>. . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 81</div><div class="t m0 x9 h7 y84 ff1 fs5 fc0 sc0 ls2d ws2d">9.1.3<span class="_ _a"> </span>LSI <span class="_"> </span>. . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. 82</div><div class="t m0 x6 hd y85 ff1 fs6 fc0 sc0 ls23 ws20">9.2<span class="_ _a"> </span>Master clock switching <span class="_ _c"> </span>. . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>83</div><div class="t m0 x9 h7 y86 ff1 fs5 fc0 sc0 ls25 ws22">9.2.1<span class="_ _a"> </span>System start<span class="_ _1"></span>up <span class="_ _9"></span>. . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . 83</div><div class="t m0 x9 h7 y87 ff1 fs5 fc0 sc0 ls1 ws21">9.2.2<span class="_ _a"> </span>Master c<span class="_ _1"></span>lock switching procedures <span class="_ _9"></span> . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 83</div><div class="t m0 x6 hd y88 ff1 fs6 fc0 sc0 ls23 ws20">9.3<span class="_ _a"> </span>Low-speed clock selection <span class="_ _c"> </span>. . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>86</div><div class="t m0 x6 hd y89 ff1 fs6 fc0 sc0 ls23 ws20">9.4<span class="_ _a"> </span>CPU clock-divider <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _c"> </span>86</div><div class="t m0 x6 hd y8a ff1 fs6 fc0 sc0 ls23 ws20">9.5<span class="_ _a"> </span>Peripheral clock-gating (PCG) . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . . . . . . <span class="_ _c"> </span>87</div><div class="t m0 x6 hd y8b ff1 fs6 fc0 sc0 ls23 ws20">9.6<span class="_ _a"> </span>Clock security system (CSS) <span class="_ _d"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>88</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89634253/bg5.jpg"><div class="t m0 xa h2 y1 ff1 fs0 fc0 sc0 ls33 ws34">DocID14587 Rev 14<span class="_ _2"> </span>5/467</div><div class="t m0 x1 ha y29 ff2 fs5 fc0 sc0 ls1d ws1">RM0016<span class="_ _6"> </span><span class="ls14">Contents</span></div><div class="t m0 x2 h3 y2 ff1 fs1 fc1 sc0 ls34 ws1">16</div><div class="t m0 x6 hd y6b ff1 fs6 fc0 sc0 ls23 ws20">9.7<span class="_ _a"> </span>Clock-out capability (CCO) <span class="_ _d"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _c"> </span>89</div><div class="t m0 x6 hd y6c ff1 fs6 fc0 sc0 ls19 ws1">9.8<span class="_ _a"> </span>CLK interrupts <span class="_ _8"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . <span class="_ _c"> </span>89</div><div class="t m0 x6 hd y8c ff1 fs6 fc0 sc0 ls19 ws1">9.9<span class="_ _a"> </span>CLK register description <span class="_ _9"></span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . . <span class="_ _c"> </span>90</div><div class="t m0 x9 h7 y8d ff1 fs5 fc0 sc0 ls36 ws37">9.9.1<span class="_ _a"> </span>Internal clock register (CLK_ICKR) <span class="_ _d"></span> . . . . .<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. 90</div><div class="t m0 x9 h7 y8e ff1 fs5 fc0 sc0 ls30 ws31">9.9.2<span class="_ _a"> </span>External cloc<span class="_ _1"></span>k register (CLK_ECKR) <span class="_ _e"> </span>. . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . <span class="_ _1"></span>91</div><div class="t m0 x9 h7 y8f ff1 fs5 fc0 sc0 ls36 ws37">9.9.3<span class="_ _a"> </span>Clock master st<span class="_ _1"></span>atus register (CLK_CMSR) <span class="_ _8"> </span>. . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . . 92</div><div class="t m0 x9 h7 y90 ff1 fs5 fc0 sc0 ls2e ws2f">9.9.4<span class="_ _a"> </span>Clock master sw<span class="_ _1"></span>itch register (CLK_SWR) <span class="_ _e"> </span>. <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . 92</div><div class="t m0 x9 h7 y91 ff1 fs5 fc0 sc0 ls2e ws2f">9.9.5<span class="_ _a"> </span>Switch control register (C<span class="_ _1"></span>LK_SWCR) <span class="_ _e"> </span> . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . 93</div><div class="t m0 x9 h7 y92 ff1 fs5 fc0 sc0 ls1 ws21">9.9.6<span class="_ _a"> </span>Clock divider <span class="_ _1"></span>register (CLK_CKDIVR) <span class="_ _8"> </span>.<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 94</div><div class="t m0 x9 h7 y93 ff1 fs5 fc0 sc0 ls17 ws18">9.9.7<span class="_ _a"> </span>Peripheral clock gating register 1 (C<span class="ls30 ws31">LK_PCKENR1) <span class="_ _f"> </span>. . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . 95</span></div><div class="t m0 x9 h7 y94 ff1 fs5 fc0 sc0 ls17 ws18">9.9.8<span class="_ _a"> </span>Peripheral clock gating register 2 (C<span class="ls30 ws31">LK_PCKENR2) <span class="_ _f"> </span>. . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . 96</span></div><div class="t m0 x9 h7 y95 ff1 fs5 fc0 sc0 ls40 ws47">9.9.9<span class="_ _a"> </span>Clock security sy<span class="_ _1"></span>stem register (CLK_CSSR) <span class="_ _d"></span>. . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . 97</div><div class="t m0 x9 h7 y96 ff1 fs5 fc0 sc0 ls15 ws24">9.9.10<span class="_ _12"> </span>Configurable clock output <span class="_ _4"></span><span class="ls36 ws37">register (CLK_CCOR) <span class="_ _8"> </span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . 98</span></div><div class="t m0 x9 h7 y97 ff1 fs5 fc0 sc0 ls41 ws48">9.9.1<span class="_ _10"></span>1<span class="_ _13"> </span>HSI clock calibration trimming register (CLK_HSI<span class="_ _1"></span>TRIMR) <span class="_ _d"></span>. . . . . <span class="_ _1"></span>. . . . . . 99</div><div class="t m0 x9 h7 y98 ff1 fs5 fc0 sc0 ls41 ws48">9.9.12<span class="_ _12"> </span>SWIM clock control regis<span class="_ _1"></span>ter (CLK_SWIMCCR) <span class="_ _e"> </span>. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . 99</div><div class="t m0 x6 hd y99 ff1 fs6 fc0 sc0 ls19 ws1">9.10<span class="_ _14"> </span>CLK register map and reset values <span class="_ _9"></span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>100</div><div class="t m0 x1 hc y9a ff2 fs8 fc0 sc0 ls3a ws49">10<span class="_ _15"> </span>Power management <span class="_ _c"> </span> . . . . . . <span class="ls27 ws25">. . . . . . . . . . . . . . . . . <span class="ls42 ws4a">. . . . . . . . . . . . . . . . <span class="_ _9"></span>101</span></span></div><div class="t m0 x6 hd y9b ff1 fs6 fc0 sc0 ls19 ws1">10.1<span class="_ _14"> </span>General considerations <span class="_ _8"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>101</div><div class="t m0 x9 h7 y9c ff1 fs5 fc0 sc0 ls43 ws4b">10.1.1<span class="_ _12"> </span>Clock management for low consumption <span class="_ _9"></span>. . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . 102</div><div class="t m0 x6 hd y9d ff1 fs6 fc0 sc0 ls23 ws20">10.2<span class="_ _14"> </span>Low power modes <span class="_ _e"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . <span class="_ _c"> </span>102</div><div class="t m0 x9 h7 y9e ff1 fs5 fc0 sc0 ls24 ws29">10.2.1<span class="_ _12"> </span>W<span class="_ _4"></span>ait mode <span class="_ _d"></span> . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>103</div><div class="t m0 x9 h7 y9f ff1 fs5 fc0 sc0 ls25 ws22">10.2.2<span class="_ _12"> </span>Halt mode <span class="_"> </span> . . . . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>103</div><div class="t m0 x9 h7 ya0 ff1 fs5 fc0 sc0 ls1 ws21">10.2.3<span class="_ _12"> </span>Active-halt modes <span class="_ _8"> </span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . 103</div><div class="t m0 x6 hd ya1 ff1 fs6 fc0 sc0 ls23 ws20">10.3<span class="_ _14"> </span>Additional analog power controls <span class="_ _8"> </span>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>104</div><div class="t m0 x9 h7 ya2 ff1 fs5 fc0 sc0 ls44 ws4c">10.3.1<span class="_ _12"> </span>Fast Flash wakeup from Halt mode <span class="_ _f"> </span>. . . . <span class="ls11 ws3f">.<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . <span class="_ _1"></span>. . 104</span></div><div class="t m0 x9 h7 ya3 ff1 fs5 fc0 sc0 ls45 ws4d">10.3.2<span class="_ _12"> </span>V<span class="_ _10"></span>ery low Flash c<span class="_ _1"></span>onsumption in <span class="_ _10"></span>Active-halt mode <span class="_ _d"></span>. . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>104</div><div class="t m0 x1 hc ya4 ff2 fs8 fc0 sc0 ls46 ws1">1<span class="_ _10"></span>1<span class="_ _16"> </span>General purpose I/O ports (GPIO)<span class="ws44"> . . . . . . . . . <span class="ls47 ws4e">. . . . . . . . . . <span class="ls22 ws4f">. . . . . . . . . <span class="_ _9"></span>105</span></span></span></div><div class="t m0 x6 hd y85 ff1 fs6 fc0 sc0 ls19 ws1">1<span class="_ _17"></span>1.1<span class="_ _12"> </span>Introduction <span class="_"> </span> . . . . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>105</div><div class="t m0 x6 hd ya5 ff1 fs6 fc0 sc0 ls19 ws1">1<span class="_ _17"></span>1.2<span class="_ _12"> </span>GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<span class="_ _4"></span> . . . . . . . <span class="_ _c"> </span>105</div><div class="t m0 x6 hd ya6 ff1 fs6 fc0 sc0 ls39 ws3b">1<span class="_ _17"></span>1.3<span class="_ _12"> </span>Port configuration and usage <span class="_ _c"> </span>. . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . <span class="_ _8"> </span>106</div><div class="t m0 x9 h7 ya7 ff1 fs5 fc0 sc0 ls11 ws3f">1<span class="_ _17"></span>1.3.1<span class="_ _18"> </span>Input modes <span class="_ _f"> </span>. .<span class="_ _1"></span> . . . . . .<span class="_ _1"></span> . . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>107</div><div class="t m0 x9 h7 ya8 ff1 fs5 fc0 sc0 ls25 ws22">1<span class="_ _17"></span>1.3.2<span class="_ _18"> </span>Output modes <span class="_ _8"> </span> . . . . . . . .<span class="_ _1"></span> . . . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>. . . . . . . . <span class="_ _1"></span>. . . . . . .<span class="_ _1"></span> . . . . . . <span class="_ _1"></span>108</div><div class="t m0 x6 hd ya9 ff1 fs6 fc0 sc0 ls19 ws1">1<span class="_ _17"></span>1.4<span class="_ _12"> </span>Reset configuration <span class="_ _c"> </span> . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>108</div><div class="t m0 x6 hd yaa ff1 fs6 fc0 sc0 ls39 ws3b">1<span class="_ _17"></span>1.5<span class="_ _12"> </span>Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . <span class="_ _4"></span>. . . . . . . . . . . . . . . . . . <span class="_ _c"> </span>108</div><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a><a class="l"><div class="d m1"></div></a></div><div class="pi" data-data='{"ctm":[1.611639,0.000000,0.000000,1.611639,0.000000,0.000000]}'></div></div>

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