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外企笔试面试题-例题【项目资源】：包含前端、后端、移动开发、操作系统、人工智能、物联网、信息化管理、数据库、硬件开发、大数据、课程资源、音视频、网站开发等各种技术项目的源码。包括STM32、ESP8266、PHP、QT、Linux、iOS、C++、Java、python、web、C#、EDA、proteus、RTOS等项目的源码。【项目质量】：所有源码都经过严格测试，可以直接运行。功能在确认正常工作后才上传。【适用人群】：适用于希望学习不同技术领域的小白或进阶学习者。可作为毕设项目、课程设计、大作业、工程实训或初期项目立项。【附加价值】：项目具有较高的学习借鉴价值，也可直接拿来修改复刻。对于有一定基础或热衷于研究的人来说，可以在这些基础代码上进行修改和扩展，实现其他功能。【沟通交流】：有任何使用上的问题，欢迎随时与博主沟通，博主会及时解答。鼓励下载和使用，并欢迎大家互相学习，共同进步。

<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89617010/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89617010/bg1.jpg"/><div class="c x0 y1 w2 h0"><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">Comput<span class="_ _0"></span>er Ar<span class="_ _0"></span>chit<span class="_ _0"></span>ec<span class="_ _1"></span>tur<span class="_ _0"></span>e</div><div class="t m0 x2 h3 y3 ff2 fs1 fc0 sc0 ls0 ws0">Lectur<span class="_ _0"></span>e 10</div><div class="t m0 x3 h4 y4 ff2 fs2 fc1 sc0 ls0 ws0">Copyrigh<span class="_ _0"></span>t <span class="_ _1"></span>©2022 John T<span class="_ _2"></span>. O'Donnell</div><div class="t m0 x4 h5 y5 ff1 fs3 fc2 sc0 ls0 ws0">Dr José Ca<span class="_ _0"></span>no Rey<span class="_ _0"></span>es</div><div class="t m0 x5 h6 y6 ff2 fs4 fc2 sc0 ls0 ws0">School of Computing <span class="_ _0"></span>Science</div><div class="t m0 x6 h6 y7 ff2 fs4 fc2 sc0 ls0 ws0">Univ<span class="_ _0"></span>er<span class="_ _3"></span>sity of Glasgo<span class="_ _0"></span>w</div><div class="t m0 x7 h6 y8 ff2 fs4 fc2 sc0 ls0 ws0">Autumn 2022</div><div class="t m0 x8 h7 y9 ff3 fs5 fc3 sc0 ls0 ws0">Processor<span class="_"> </span>Datapath</div></div></div><div class="pi" data-data='{"ctm":[1.000000,0.000000,0.000000,1.000000,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89617010/bg2.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x9 h8 ya ff3 fs6 fc3 sc0 ls0 ws0">Outline</div><div class="t m0 x9 h9 yb ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">Datapath and Control</span></div><div class="t m0 x9 ha yc ff4 fs8 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">Processo<span class="_ _0"></span>r <span class="_ _1"></span>Datapath</span></div><div class="t m0 xa h9 yd ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Regi<span class="_ _0"></span>sters</span></div><div class="t m0 xa h9 ye ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Internal<span class="_ _0"></span> <span class="_ _1"></span>processor signals</span></div><div class="t m0 xa h9 yf ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Interface</span></div><div class="t m0 x9 h9 y10 ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">Operating the datapath</span></div><div class="t m0 xa h9 y11 ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Writing the<span class="_ _3"></span> ir</span></div><div class="t m0 xa ha y12 ff4 fs8 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Fetchin<span class="_ _0"></span>g <span class="_ _1"></span>an instruc<span class="_ _0"></span>tion and incrementing pc</span></div><div class="t m0 xa h9 y13 ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Using<span class="_ _0"></span> <span class="_ _1"></span>the register file</span></div><div class="t m0 xb hb y14 ff3 fs2 fc1 sc0 ls0 ws0">2</div></div></div><div class="pi" data-data='{"ctm":[1.000000,0.000000,0.000000,1.000000,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89617010/bg3.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x9 h8 ya ff6 fs6 fc3 sc0 ls0 ws0">Where we are going…</div><div class="t m0 x9 hc yb ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="fc0">We’ll describe a digital<span class="_ _0"></span> <span class="_ _1"></span>circuit (M1) that implements the Sigma16 architecture</span></div><div class="t m0 xa h9 y15 ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">It w<span class="_ _0"></span>ill <span class="_ _1"></span>be specified in full detail<span class="_ _0"></span> <span class="_ _1"></span>(i.e. level of logic gates and flip flops)</span></div><div class="t m0 x9 hc yd ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="fc0">No “magic” black box<span class="_ _3"></span>es</span></div><div class="t m0 xa h9 ye ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">The de<span class="_ _3"></span>sign contains just logi<span class="_ _3"></span>c gates and flip flops</span></div><div class="t m0 x9 ha y16 ff4 fs8 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">We w<span class="_ _0"></span>ill <span class="_ _1"></span>have tw<span class="_ _0"></span>o <span class="_ _1"></span>w<span class="_ _0"></span>a<span class="_ _1"></span>y<span class="_ _0"></span>s <span class="_ _5"></span>of ex<span class="_ _0"></span>ecuting <span class="_ _1"></span>a Sigma16<span class="_ _0"></span> <span class="_ _1"></span>program</span></div><div class="t m0 xa h9 y17 ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Using<span class="_ _0"></span> <span class="_ _1"></span><span class="fc4">the Sigma16 emulator </span>(interprets the machine lang<span class="_ _0"></span>uage, <span class="_ _1"></span>w<span class="_ _0"></span>ith <span class="_ _5"></span>lo<span class="_ _0"></span>ts of visual feedback in a </span></div><div class="t m0 xc h9 y18 ff5 fs7 fc2 sc0 ls0 ws0">GUI)</div><div class="t m0 xa ha y19 ff4 fs8 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Ru<span class="_ _3"></span>nning<span class="_ _0"></span> <span class="_ _1"></span>it on<span class="_"> </span><span class="fc4">the M1 circuit<span class="_"> </span></span>(read<span class="_ _0"></span>ing <span class="_ _1"></span>in the mach<span class="_ _0"></span>ine <span class="_ _1"></span>code, storin<span class="_ _3"></span>g it in memory<span class="_ _0"></span>, <span class="_ _1"></span>and then ex<span class="_ _3"></span>ecuting<span class="_ _0"></span> </span></div><div class="t m0 xc h9 y1a ff5 fs7 fc2 sc0 ls0 ws0">the program)</div><div class="t m0 xb hb y14 ff3 fs2 fc1 sc0 ls0 ws0">3</div></div></div><div class="pi" data-data='{"ctm":[1.000000,0.000000,0.000000,1.000000,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89617010/bg4.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x9 h8 ya ff3 fs6 fc3 sc0 ls0 ws0">Plan</div><div class="t m0 x9 hc yb ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="fc0">The RTM circuit can ex<span class="_ _3"></span>ecute only 1 RRR instruction (add)… now<span class="_ _0"></span> <span class="_ _5"></span>w<span class="_ _0"></span>e need to do the rest!</span></div><div class="t m0 x9 ha yc ff4 fs8 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">We start w<span class="_ _0"></span>ith <span class="_ _1"></span>a <span class="fc4">basic datap<span class="_ _3"></span>ath<span class="_"> </span><span class="fc0">for Sigma16</span></span></span></div><div class="t m0 xa h9 yd ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Just w<span class="_ _0"></span>hat's required to execute (the core part of) the instruction set</span></div><div class="t m0 x9 h9 yf ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="fc0">Then w<span class="_ _0"></span>e’ll <span class="_ _1"></span>add the rest of a basic system:<span class="_"> </span><span class="ff5 fc4">control<span class="_"> </span><span class="fc0 ls1">and <span class="_ _1"></span></span><span class="ls2">I/O </span></span></span></div><div class="t m0 x9 hc y10 ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="fc0">Then w<span class="_ _0"></span>e’ll <span class="_ _1"></span>look at some more sophisticated techniqu<span class="_ _0"></span>es </span></div><div class="t m0 xa h9 y11 ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Describ<span class="_ _0"></span>ed <span class="_ _1"></span>at higher level, w<span class="_ _0"></span>ithout <span class="_ _1"></span>every detail implemented<span class="_ _0"></span> <span class="_ _1"></span>at circuit level</span></div><div class="t m0 xa hd y12 ff4 fs8 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff7 fc2">Exa<span class="_ _0"></span>mples<span class="ff5">: Cache, Pipelin<span class="_ _3"></span>ing, Superscala<span class="_ _0"></span>r</span></span></div><div class="t m0 xb hb y14 ff3 fs2 fc1 sc0 ls0 ws0">4</div></div></div><div class="pi" data-data='{"ctm":[1.000000,0.000000,0.000000,1.000000,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/89617010/bg5.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x9 h8 ya ff3 fs6 fc3 sc0 ls0 ws0">Datapath and control</div><div class="t m0 x9 h9 yb ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">Large circuits are organise<span class="_ _0"></span>d <span class="_ _1"></span>into tw<span class="_ _0"></span>o <span class="_ _1"></span>major subsystems: <span class="_ _1"></span><span class="fc4">datapath<span class="_"> </span></span><span class="ls1">and </span><span class="fc4">control</span></span></div><div class="t m0 xa he y15 ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff7 fc2">Exam<span class="_ _0"></span>pl<span class="_ _1"></span>e<span class="ff5">: processor (CPU)</span></span></div><div class="t m0 x9 he ye ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff7 fc0">Datapath circuit<span class="ff5">: contains <span class="fc4">registers<span class="_"> </span></span><span class="ls3">and </span><span class="fc4">combinationa<span class="_ _0"></span>l <span class="_ _1"></span>logic <span class="fc0">for calculations</span></span></span></span></div><div class="t m0 x9 he y10 ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff7 fc0">Control circuit<span class="ff5 ls2">: <span class="fc4 ls0">gene<span class="_ _0"></span>rates<span class="_ _6"> </span><span class="fc0">all the </span>control signa<span class="_ _0"></span>ls <span class="_ _1"></span><span class="fc0">needed by the datapath<span class="_"> </span>circuit</span></span></span></span></div><div class="t m0 x9 h9 y13 ff4 fs7 fc3 sc0 ls0 ws0">•<span class="_ _4"> </span><span class="ff5 fc0">Many<span class="_ _0"></span> <span class="_ _1"></span>of the components in the datapath<span class="_"> </span>require control inputs</span></div><div class="t m0 xa h9 y1b ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Regi<span class="_ _0"></span>sters <span class="_ _1"></span>take a load control input</span></div><div class="t m0 xa h9 y1c ff4 fs7 fc3 sc0 ls0 ws0">–<span class="_"> </span><span class="ff5 fc2">Multipl<span class="_ _0"></span>exers <span class="_ _1"></span>and demultiple<span class="_ _0"></span>xers <span class="_ _1"></span>take conditional inputs (i.e. addresses)</span></div><div class="t m0 xb hb y14 ff3 fs2 fc1 sc0 ls0 ws0">5</div></div></div><div class="pi" data-data='{"ctm":[1.000000,0.000000,0.000000,1.000000,0.000000,0.000000]}'></div></div>

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