ZIP2018-2022就读电子科技大学UESTC期间的各种实验报告和课程设计.zip 8.58MB

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资源文件列表:

2018-2022就读电子科技大学UESTC期间的各种实验报告和课程设计.zip 大约有33个文件
  1. Graduation Design/FPGA综合实验报告3.pdf 2.21MB
  2. Graduation Design/实验七_基于FPGA的BPSK信号产生器设计/关于BPSK和QPSK.pdf 233.67KB
  3. Graduation Design/实验七_基于FPGA的BPSK信号产生器设计/实验七_基于FPGA的BPSK信号产生器设计(实验指导书).pdf 355.92KB
  4. Graduation Design/实验二 基于FPGA的时钟秒表/实验二_三_时钟及秒表设计(实验指导书).pdf 691.05KB
  5. Graduation Design/实验二 基于FPGA的时钟秒表/按键消抖.v 829B
  6. Graduation Design/实验二 基于FPGA的时钟秒表/课堂讨论作业.pptx 38.94KB
  7. Graduation Design/实验二 基于FPGA的时钟秒表/时钟所需文件/adjust_test.v 215B
  8. Graduation Design/实验二 基于FPGA的时钟秒表/时钟所需文件/auto_reset.v 492B
  9. Graduation Design/实验二 基于FPGA的时钟秒表/时钟所需文件/bin_dec.v 2.37KB
  10. Graduation Design/实验二 基于FPGA的时钟秒表/时钟所需文件/myclock.v 1.65KB
  11. Graduation Design/实验二 基于FPGA的时钟秒表/时钟所需文件/SEG7_LUT.v 708B
  12. Graduation Design/实验五_基于FPGA PN码序列产生器设计/PN_1023_gen_1.v 1.69KB
  13. Graduation Design/实验五_基于FPGA PN码序列产生器设计/实验五_基于FPGA PN码序列产生器设计(实验指导书).pdf 392.74KB
  14. Graduation Design/实验五_基于FPGA PN码序列产生器设计/扩频通信技术在通信中的研究.caj 1.06MB
  15. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关.zip 19.62KB
  16. Graduation Design/实验六_基于FPGA的DDS设计/实验六_基于FPGA的DDS设计(实验指导书).pdf 498.86KB
  17. Graduation Design/实验六_基于FPGA的DDS设计/实验六_基于FPGA的DDS设计.pptx 927.14KB
  18. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/autoreset.v 492B
  19. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/DDS_ACC.v 327B
  20. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/romcos.bsf 2.06KB
  21. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/romcos.tdf 5.44KB
  22. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/romcos12x8.mif 56.08KB
  23. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/romsin12x8.mif 56.08KB
  24. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/sinrom.bsf 2.06KB
  25. Graduation Design/实验六_基于FPGA的DDS设计/DDS相关/sinrom.tdf 5.44KB
  26. Graduation Design/实验四 基于FPGA的LCD显示器/1602LCD使用说明书及模块代码C-免费下载.pdf 634.17KB
  27. Graduation Design/实验四 基于FPGA的LCD显示器/CFAH1602BTMCJP.pdf 237.79KB
  28. Graduation Design/实验四 基于FPGA的LCD显示器/LCD_Controller.v 1.01KB
  29. Graduation Design/实验四 基于FPGA的LCD显示器/LCD_TEST.v 3.08KB
  30. Graduation Design/实验四 基于FPGA的LCD显示器/LCD实验参考文件.zip 783.72KB
  31. Graduation Design/实验四 基于FPGA的LCD显示器/Reset_Delay.v 233B
  32. Graduation Design/实验四 基于FPGA的LCD显示器/实验四_基于FPGA的LCD显示系统设计(课程用实验指导书).pdf 824.93KB
  33. Graduation Design/实验四 基于FPGA的LCD显示器/实验四状态机及指令分析.pdf 585.1KB

资源介绍:

课程设计报告
<link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/base.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/css/fancy.min.css" rel="stylesheet"/><link href="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90150603/2/raw.css" rel="stylesheet"/><div id="sidebar" style="display: none"><div id="outline"></div></div><div class="pf w0 h0" data-page-no="1" id="pf1"><div class="pc pc1 w0 h0"><img alt="" class="bi x0 y0 w1 h1" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90150603/bg1.jpg"/><div class="c x0 y1 w2 h0"><div class="t m0 x1 h2 y2 ff1 fs0 fc0 sc0 ls0 ws0">FPGA<span class="_ _0"> </span><span class="ff2">综合实验<span class="_ _1"></span>报告<span class="_ _0"> </span><span class="ff1">3 </span></span></div><div class="t m0 x2 h3 y3 ff2 fs1 fc0 sc0 ls0 ws0">周子涵<span class="ff1"> <span class="_ _2"> </span>201<span class="_ _1"></span>8<span class="_ _3"></span>011218014 </span></div><div class="t m0 x3 h3 y4 ff2 fs1 fc0 sc0 ls0 ws0">一、题目需求分析<span class="ff1"> </span></div><div class="t m0 x3 h3 y5 ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _2"> </span><span class="ls1"> </span><span class="ff2">利用<span class="_ _2"> </span></span>V<span class="_ _3"></span>erilog<span class="_ _4"> </span><span class="ff2">语言编程，在<span class="_ _2"> </span></span>FP<span class="_ _3"></span>GA<span class="_ _2"> </span><span class="ff2">中产生两路伪随机码，通过改变其中一路</span></div><div class="t m0 x3 h3 y6 ff2 fs1 fc0 sc0 ls0 ws0">伪<span class="ff1"> <span class="_ _2"> </span></span>随机码的初相，验证<span class="_ _2"> </span><span class="ff1 ls2">PN<span class="_ _2"> </span></span>码的特性，体会直<span class="_ _3"></span>接序列扩频通信系统的基本特</div><div class="t m0 x3 h3 y7 ff2 fs1 fc0 sc0 ls0 ws0">点。<span class="ff1"> </span></div><div class="t m0 x3 h3 y8 ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _2"> </span><span class="ls1"> </span><span class="ff2">利用<span class="_ _2"> </span></span>V<span class="_ _3"></span>erilog<span class="_ _4"> </span><span class="ff2">语言、在<span class="_ _2"> </span></span>Qu<span class="_ _3"></span>artus<span class="_ _2"> </span><span class="ff2">软件中，使用<span class="_ _4"> </span></span>LPM<span class="_ _4"> </span><span class="ff2">模块、</span>IPcore<span class="_"> </span><span class="ff2">等模块，在</span></div><div class="t m0 x3 h3 y9 ff1 fs1 fc0 sc0 ls0 ws0">FPGA <span class="_ _2"> </span><span class="ff2">中设计一种数字频率直接合成器。可以通过改变<span class="_ _4"> </span></span><span class="ls3">DDS<span class="_"> </span></span><span class="ff2">的初值，改变系统</span></div><div class="t m0 x3 h3 ya ff2 fs1 fc0 sc0 ls0 ws0">时钟得到<span class="ff1"> <span class="_ _2"> </span></span>工程需要的不同频率信号源。利用<span class="_ _4"> </span><span class="ff1">SignalTap<span class="_"> </span></span>验证<span class="_ _2"> </span><span class="ff1 ls3">DDS<span class="_"> </span></span>生成的信号频</div><div class="t m0 x3 h3 yb ff2 fs1 fc0 sc0 ls0 ws0">率，并将之与<span class="ff1"> <span class="_ _2"> </span>sin<span class="_ _2"> </span></span>表的查找表文件比较。<span class="_ _3"></span><span class="ff1"> </span></div><div class="t m0 x3 h3 yc ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _2"> </span><span class="ls1"> </span><span class="ff2">调整<span class="_ _2"> </span></span>P<span class="_ _3"></span>LL<span class="_ _2"> </span><span class="ff2">分倍频系数，生成合适的时钟频率，分别用<span class="_ _4"> </span></span>IPc<span class="_ _3"></span>ore<span class="_ _4"> </span><span class="ff2">和自编模块设</span></div><div class="t m0 x3 h3 yd ff2 fs1 fc0 sc0 ls0 ws0">计<span class="ff1"> <span class="_ _2"> </span><span class="ls3">DDS</span></span>，产生<span class="_ _4"> </span><span class="ff1">2<span class="_ _3"></span>5MHz<span class="_ _2"> </span></span>的单频信号。设计<span class="_ _4"> </span><span class="ff1 ls4">PN<span class="_ _2"> </span></span>码模块，产生<span class="_ _2"> </span><span class="ff1">Go<span class="_ _3"></span>ld<span class="_ _2"> </span></span>码序列（<span class="ff1">Gold</span></div><div class="t m0 x3 h3 ye ff2 fs1 fc0 sc0 ls0 ws0">码序列<span class="ff1"> <span class="_ _2"> </span></span>的生成多项式、初相参考实验五内容）<span class="_ _5"></span>。设计模拟串行信号产生模块，</div><div class="t m0 x3 h3 yf ff2 fs1 fc0 sc0 ls0 ws0">将此串行<span class="ff1"> <span class="_ _2"> </span></span>信号用<span class="_ _2"> </span><span class="ff1 ls2">PN<span class="_ _2"> </span></span>码扩频。应用<span class="_ _4"> </span><span class="ff1">BPS<span class="_ _3"></span>K<span class="_ _2"> </span></span>调制<span class="_ _3"></span>原理，将扩频后的串行信号调制</div><div class="t m0 x3 h3 y10 ff2 fs1 fc0 sc0 ls0 ws0">在<span class="_ _2"> </span><span class="ff1">25MHz<span class="_ _2"> </span></span>的载<span class="_ _3"></span><span class="ff1"> <span class="_ _2"> </span></span>波上。<span class="ff1"> </span></div><div class="t m0 x3 h3 y11 ff2 fs1 fc0 sc0 ls0 ws0">二、顶层设计<span class="ff1"> </span></div><div class="t m0 x3 h3 y12 ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _2"> </span><span class="ls1"> <span class="ls2">PN<span class="_ _2"> </span></span></span><span class="ff2">码及<span class="_ _2"> </span></span>D<span class="_ _3"></span><span class="ls3">DS<span class="_"> </span></span><span class="ff2">的设计如下图：</span> </div><div class="t m0 x4 h3 y13 ff1 fs1 fc0 sc0 ls0 ws0"> </div></div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div><div id="pf2" class="pf w0 h0" data-page-no="2"><div class="pc pc2 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90150603/bg2.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x3 h3 y14 ff2 fs1 fc0 sc0 ls0 ws0">&#39318;&#20808;&#29983;&#25104;&#26102;&#38047;&#21644;&#19978;&#30005;&#22797;&#20301;&#27169;&#22359;&#65292;&#29983;&#25104;&#19968;&#20010;<span class="_ _4"> </span><span class="ff1">PN<span class="_"> </span></span>&#30721;&#24207;&#21015;&#65292;&#28982;&#21518;&#26500;&#24314;&#19968;&#20010;&#26032;&#30340;<span class="_ _2"> </span><span class="ff1">PN<span class="_ _2"> </span></span>&#30721;</div><div class="t m0 x3 h3 y3 ff2 fs1 fc0 sc0 ls0 ws0">&#24207;&#21015;&#65292;&#23558;&#20004;&#32773;&#36827;&#34892;&#27169;<span class="_ _2"> </span><span class="ff1">2<span class="_ _4"> </span></span>&#21152;&#65292;&#24471;<span class="_ _3"></span>&#21040;<span class="_ _2"> </span><span class="ff1">gold<span class="_"> </span></span>&#30721;&#24207;&#21015;&#65292;&#22797;&#21046;&#19968;&#20010;<span class="_ _2"> </span><span class="ff1">gold<span class="_"> </span></span>&#30721;&#24207;&#21015;&#65292;&#20462;&#25913;&#21021;</div><div class="t m0 x3 h3 y4 ff2 fs1 fc0 sc0 ls0 ws0">&#30456;&#65292;&#23558;&#20004;&#32773;&#36827;&#34892;&#24322;&#25110;&#65292;&#29983;&#25104;&#30456;&#20301;&#32047;&#21152;&#22120;&#21644;&#27874;&#22411;&#23384;&#20648;&#22120;&#65292;&#25130;&#21462;&#30456;&#20301;&#32047;&#21152;&#22120;&#30340;&#39640;<span class="ff1"> <span class="_ _2"> </span><span class="ls5">12 </span></span></div><div class="t m0 x3 h3 y5 ff2 fs1 fc0 sc0 ls0 ws0">&#20301;&#20316;&#20026;&#27874;&#24418;&#23384;&#20648;&#22120;&#30340;&#26597;&#34920;&#22320;&#22336;&#20301;&#12290;<span class="ff1"> </span></div><div class="t m0 x3 h3 y6 ff1 fs1 fc0 sc0 ls0 ws0"> <span class="_ _2"> </span><span class="ls1"> </span>BPSK<span class="_"> </span><span class="ff2">&#30340;&#35774;&#35745;&#22914;&#19979;&#22270;&#65306;<span class="_ _1"></span><span class="ff1"> </span></span></div><div class="t m0 x5 h3 y15 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3 h3 yf ff2 fs1 fc0 sc0 ls0 ws0">&#39318;&#20808;&#29983;&#25104;&#26102;&#38047;&#21644;&#19978;&#30005;&#22797;&#20301;&#27169;&#22359;&#65292;&#22312;<span class="_ _2"> </span><span class="ff1">P<span class="_ _3"></span>N<span class="_ _2"> </span></span>&#30721;&#21644;<span class="_ _4"> </span><span class="ff1">D<span class="ls6">DS<span class="_ _2"> </span></span></span>&#30340;&#22522;&#30784;&#19978;&#65292;&#29992;<span class="_ _4"> </span><span class="ff1">T<span class="_"> </span></span>&#35302;&#21457;&#22120;&#20135;&#29983;</div><div class="t m0 x3 h3 y10 ff1 fs1 fc0 sc0 ls5 ws0">0,<span class="ls0">1<span class="_ _2"> </span><span class="ff2">&#24207;&#21015;&#20316;&#20026;&#35843;&#21046;&#20449;&#24687;&#65292;&#20135;&#29983;&#20219;&#24847;&#20018;&#34892;&#26102;&#38047;&#20449;<span class="_ _3"></span>&#21495;&#65292;&#23558;<span class="_ _4"> </span></span>gold<span class="_"> </span><span class="ff2">&#30721;&#19982;&#35843;&#21046;&#20449;&#24687;&#27169;&#20108;</span></span></div><div class="t m0 x3 h3 y11 ff2 fs1 fc0 sc0 ls0 ws0">&#21152;&#65292;&#22312;&#30456;&#20301;&#32047;&#21152;&#22120;&#12289;<span class="ff1">sin <span class="_ _2"> </span></span>&#34920;&#12289;<span class="ff1">cos <span class="_ _2"> </span></span>&#34920;&#27169;&#22359;&#20013;&#65292;&#21033;&#29992;&#35843;&#21046;&#20449;&#21495;&#25913;&#21464;&#26597;&#25214;<span class="ff1"> <span class="_ _2"> </span></span>&#34920;&#30340;&#22320;&#22336;</div><div class="t m0 x3 h3 y12 ff2 fs1 fc0 sc0 ls0 ws0">&#20449;&#21495;&#26368;&#39640;&#20301;&#65292;&#23454;&#29616;&#30456;&#20301;&#35843;&#25972;&#65292;&#20063;&#21487;&#20197;&#23454;&#29616;<span class="ff1"> <span class="_ _2"> </span>BPSK <span class="_ _2"> </span></span>&#20449;&#21495;&#35843;&#21046;&#12290;<span class="ff1"> </span></div><div class="t m0 x3 h3 y16 ff2 fs1 fc0 sc0 ls0 ws0">&#19977;&#12289;&#23454;&#39564;&#21407;&#29702;<span class="ff1"> </span></div><div class="t m0 x3 h3 y17 ff1 fs1 fc0 sc0 ls0 ws0">PN<span class="_ _2"> </span><span class="ff2">&#30721;&#65306;</span> </div></div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div><div id="pf3" class="pf w0 h0" data-page-no="3"><div class="pc pc3 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90150603/bg3.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x5 h3 y18 ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 h3 y19 ff1 fs1 fc0 sc0 ls0 ws0"> </div></div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div><div id="pf4" class="pf w0 h0" data-page-no="4"><div class="pc pc4 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90150603/bg4.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x5 h3 y1a ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x3 h3 y8 ff1 fs1 fc0 sc0 ls0 ws0">D<span class="ls3">DS</span><span class="ff2">&#65306;</span> </div><div class="t m0 x5 h3 y1b ff1 fs1 fc0 sc0 ls0 ws0"> </div></div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div><div id="pf5" class="pf w0 h0" data-page-no="5"><div class="pc pc5 w0 h0"><img class="bi x0 y0 w1 h1" alt="" src="/image.php?url=https://csdnimg.cn/release/download_crawler_static/90150603/bg5.jpg"><div class="c x0 y1 w2 h0"><div class="t m0 x5 h3 y1c ff1 fs1 fc0 sc0 ls0 ws0"> </div><div class="t m0 x5 h3 y1d ff1 fs1 fc0 sc0 ls0 ws0"> </div></div></div><div class="pi" data-data='{"ctm":[1.611792,0.000000,0.000000,1.611792,0.000000,0.000000]}'></div></div>
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